Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

EDA_RTL_TEST_BENCH_NAME

Specifies the name of top-level test bench in RTL simulation test bench file.

Type

String

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

The value of this assignment is case sensitive.

Syntax

set_global_assignment -name EDA_RTL_TEST_BENCH_NAME -section_id <section identifier> <value>
set_global_assignment -name EDA_RTL_TEST_BENCH_NAME -entity <entity name> -section_id <section identifier> <value>