Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

EDA_GENERATE_SDF_FOR_POWER

Enable generation of SDO file containing delay estimates back-annotated on design netlist for improved accuracy of power estimates. This is only supported for Verilog Output simulation in ModelSim

Type

Boolean

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

None

Syntax

set_global_assignment -name EDA_GENERATE_SDF_FOR_POWER -section_id <section identifier> <value>
set_global_assignment -name EDA_GENERATE_SDF_FOR_POWER -entity <entity name> -section_id <section identifier> <value>

Default Value

Off, requires section identifier