Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

EDA_FORCE_GATE_LEVEL_REG_INIT_X

Modifies output gate level simulation netlist to force all registers to initialize to X (don't care) and propagate X

Type

Boolean

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

This assignment is included in the Fitter report.

Syntax

set_global_assignment -name EDA_FORCE_GATE_LEVEL_REG_INIT_X -section_id <section identifier> <value>
set_global_assignment -name EDA_FORCE_GATE_LEVEL_REG_INIT_X -entity <entity name> -section_id <section identifier> <value>

Default Value

Off, requires section identifier