Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

DRC_DEADLOCK_STATE_LIMIT

Specifies the maximum number of states that you want the Design Assistant to detect as a deadlock condition. A larger number will results in longer processing time.

Type

Integer

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Syntax

set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT <value>

Default Value

2