Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

STA_POST_SYN_DELAY_MODEL

Selects the post syn timing model for interconnect delays

Type

Enumeration

Values

  • Average Value
  • ML Predicted Value
  • Zero Value

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Syntax

set_global_assignment -name STA_POST_SYN_DELAY_MODEL <value>

Default Value

Average Value