Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

STA_AUTO_UPDATE_TIMING_NETLIST

Directs the Timing Analyzer to automatically create the timing netlist, read SDC constraints, and update the timing netlist whenever this project is opened in an interactive Timing Analyzer session.

Type

Boolean

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Syntax

set_global_assignment -name STA_AUTO_UPDATE_TIMING_NETLIST <value>

Default Value

On