Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS

Cuts the paths between registers clocked by unrelated clocks. This option makes the timing analysis reporting similar to MAX+PLUS II timing analysis reporting.

Type

Boolean

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

None

Syntax

set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS <value>

Default Value

On