Intel® Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 12/04/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

EDA_RTL_TEST_BENCH_FILE_NAME

Specifies the RTL simulation test bench file name for Test Bench Mode. File type can be a VHDL Test Bench File (.vht), VHDL File (.vhd), Verilog HDL Test Bench File (.vt), or Verilog HDL file (.v).

Type

File name

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

The value of this assignment is case sensitive.

Syntax

set_global_assignment -name EDA_RTL_TEST_BENCH_FILE_NAME -section_id <section identifier> <value>
set_global_assignment -name EDA_RTL_TEST_BENCH_FILE_NAME -entity <entity name> -section_id <section identifier> <value>