F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

ID 683287
Date 7/06/2024
Public
Document Table of Contents

3.7.2. Toolkit GUI Settings

The F-Tile Serial Lite IV IP toolkit offers an easy-to-manage user interface.
The F-Tile Serial Lite IV IP toolkit user interface has three tabs.
  • The MAC and PCS tab implements various control and status registers (CSR) for both the hardened custom PCS core and the MAC soft logic.
  • The Traffic Statistics tab implements various Control and Status Registers (CSR) for the Demo Management module to configure the traffic generator and checker.
  • The Help tab provides useful next-step troubleshooting information based on the assertion and deassertion of specific status registers or output ports if any errors happen after the link initialization is executed.

The MAC and PCS tab shows a step-by-step guide for link initialization and real-time status monitoring of a F-Tile Serial Lite IV IP link.

The toolkit continuously reads and displays all of the essential status registers related to the F-Tile Serial Lite IV IP link after you execute the following stages:

  1. Click Assert system reset to perform a system reset.
  2. Click Deassert system reset to finish resetting the system.
  3. Click Link initialization to perform link initialization.
  4. Click Read status to poll all corresponding status registers and output ports from both hardened custom PCS and MAC soft logic.
Figure 16. MAC and PCS Tab
Note: The toolkit user interface changes dynamically to illustrate each execution stage.

In case of any failure, the toolkit narrows down to the type of failure based on the various status bits, which are based on the register bank or output port from the hardened custom PCS core or MAC soft logic. The corresponding next-step debugging information is displayed in the Help tab.

Figure 17. Traffic Statistics Tab
The Traffic statistics tab enables you to configure both the traffic generator and checker in the design example to run in the user-specified traffic mode, and reads traffic statistics. You can also read the traffic statistics in this tab.
Note: Select only continuous mode traffic for Deterministic Latency Enabled design.
Figure 18. Help Tab

The Help tab provides useful next-step debugging information based on the errors or status registers reported from the MAC and PCS status in the MAC and PCS tab.