F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 683287
Date 7/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for F-Tile Serial Lite IV Design Example 4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives 5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for F-Tile Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. F-Tile Serial Lite IV IP Toolkit 3.8. Analog Parameters 3.9. Deterministic Latency
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.7. F-Tile Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
3.9. Deterministic Latency x
3.9.1. SYSREF Pulse Generator 3.9.2. TX DL Shim Wrapper 3.9.3. RX DL Shim Wrapper 3.9.4. Deterministic Latency Design Considerations
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for F-Tile Serial Lite IV Design Example
4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives
5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

2.1. Design Example Block Diagram

Figure 2. High-Level Block Diagram for Agilex™ 7 Design Examples
Table 3.  Design Example Components
Component Description
F-Tile Serial Lite IV Intel® FPGA IP

The F-Tile Serial Lite IV Intel® FPGA IP in this design example supports streaming or packet transfer mode with the following features:

  • For FHT transceiver type:

    • 48 Gbps to 58 Gbps and 96 Gbps to 116 Gbps per lane with a maximum of four PAM4 lanes.
    • 24 Gbps to 29 Gbps and 48 Gbps to 58 Gbps per lane with a maximum of four NRZ lanes.
  • For FGT transceiver type:
    • 20 Gbps to 58 Gbps per lane with a maximum of 12 PAM4 lanes.
    • 1 Gbps to 32 Gbps per lane with a maximum of 16 NRZ lanes for duplex and simplex designs.

The F-Tile Serial Lite IV Intel® FPGA IP accepts data from the traffic generator and formats the data for transmission.

The F-Tile Serial Lite IV Intel® FPGA IP also receives data from the link, strips the headers, and sends it to the traffic checker for analysis.

You generate the IP using the parameter editor in the Quartus® Prime Pro Edition software.

System Console

The System Console is an Quartus® Prime tool that provides a user-friendly interface for you to do first-level debugging and monitor the status of the IP, and the traffic generator, and checker.

Demo control The demo control module consists of Avalon® memory-mapped pipeline bridges connected to the transceiver reconfiguration and the demo management interfaces. The design also instantiates the JTAG master, parallel input/output (PIO), and ISSP (In-system Source and Probe) modules for System Console debugging purposes.
Demo management

The demo management module implements control and status registers (CSRs) to control, monitor the design operation, and log errors that occur during the operation.

User clock—IOPLL

For Agilex™ 7 F-tile devices, the design example uses an IOPLL to generate a user clock to transmit data to the F-Tile Serial Lite IV IP.

The design uses the iopll_ref_clk clock signal as an IOPLL reference clock to connect to the clock generator.

Important: The iopll_ref_clk should have the same frequency as the pll_refclk and come from the same clock module.
Traffic generator

The traffic generator generates traffic in a deterministic format to verify that the link transmits data correctly.
Traffic checker

The traffic checker performs inspections to verify that the received data is in the expected format.
Dual-clock FIFO (DCFIFO)

The DCFIFO blocks handle data streaming and control signals for clock crossing between different clock domains.
System PLL The system PLL drives the F-Tile Serial Lite IV Duplex and Simplex module and is driven to the same frequency as the iopll_ref_clk clock signal.
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