F-Tile CPRI PHY Intel® FPGA IP User Guide

Download PDF
ID 683284
Date 6/21/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the F-Tile CPRI PHY Intel® FPGA IP Core 2. Getting Started 3. IP Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile CPRI PHY Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide
1. About the F-Tile CPRI PHY Intel® FPGA IP Core x
1.1. Supported Features 1.2. Overview 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. IP Core Testbenches
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency 4.2.2. Calculation for 64b/66b Datapath
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. TX MII Interface (64b/66b) 5.4. RX MII Interface (64b/66b) 5.5. Status Interface for 64b/66b Line Rate 5.6. TX Interface (8b/10b) 5.7. RX Interface (8b/10b) 5.8. Status Interface for 8b/10b Line Rate 5.9. Serial Interface 5.10. CPRI PHY Reconfiguration Interface 5.11. Datapath Avalon Memory-Mapped Interface 5.12. PMA Avalon Memory-Mapped Interface
5.1. Clock Signals x
5.1.1. Required Clock Frequencies
1. About the F-Tile CPRI PHY Intel® FPGA IP Core
2. Getting Started
3. IP Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile CPRI PHY Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide

5.12. PMA Avalon Memory-Mapped Interface

Table 28.  PMA Avalon Memory-Mapped Interface Signals
Port Name Width Domain Description
i_reconfig_xcvr_addr[17:0] 18 i_reconfig_clk Address for the PMA Avalon Memory-Mapped Interface CSRs in the selected channel. Using word addressing format.
i_reconfig_xcvr_read 1 i_reconfig_clk Read command for the PMA Avalon Memory-Mapped Interface CSRs in selected the channel.
i_reconfig_xcvr_write 1 i_reconfig_clk Write command for the PMA Avalon Memory-Mapped Interface CSRs in the selected channel.
o_reconfig_xcvr_readdata[31:0] 32 i_reconfig_clk Read data from reads to the PMA Avalon Memory-Mapped Interface CSRs in the selected channel.
o_reconfig_xcvr_readdatavalid 1 i_reconfig_clk Read data from the PMA Avalon Memory-Mapped Interface CSRs is valid in the selected channel.
i_reconfig_xcvr_writedata[31:0] 32 i_reconfig_clk Data for writes to the PMA Avalon Memory-Mapped Interface CSRs in the selected channel.
o_reconfig_xcvr_waitrequest 1 i_reconfig_clk Avalon® memory-mapped interface stalling signal for operations on the PMA Avalon Memory-Mapped Interface CSRs in the selected channel.
i_reconfig_xcvr_byteenable[3:0] 4 i_reconfig_clk Byte-enable for the PMA Avalon Memory-Mapped Interface CSRs in the selected channel.
Level Two Title