DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 10/20/2022
Public

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5.1. IP to Transceiver Parallel Data Interface Width

Figure 14. DisplayPort 2.0 Source High Level Block Diagram

DP 8B/10B Channel Coding has a native symbol size of 10-bits. This value multiplied by the SYMBOLS_PER_CLOCK parameter determines the size of the IP parallel data interface to the Transceiver (XCVR). Therefore, the DP1.4 datapath in the IP, configured with QUAD SYMBOLS_PER_CLOCK, has a 40-bit wide parallel data interface to the transceiver.

DP 128B/132B Channel Coding has a native 32/64-bit symbol size, which is multiplied by 2 depending on link rates. Therefore, the DP2.0 datapath in the IP has a 32-bit or 64-bit wide parallel data interface to the transceiver.

Given that DP2.0 is backward compatible with DP1.4, and that selecting UHBR10 link rates requires all link rates below that to be supported (RBR, HBR, HBR2, HBR3); the 40-bit wide DP1.4 interface and 32/64-bit wide DP2.0 interface is then muxed internally before being sent as an output from the IP. At the IP interface level, either a 40-bit wide or 64-bit wide parallel data interface is declared as required.