DMA Accelerator Functional Unit User Guide: Intel® FPGA Programmable Acceleration Card D5005

Download PDF
ID 683270
Date 8/03/2020
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. DMA AFU Description 3. Register Map and Address Spaces 4. Software Programming Model 5. Running DMA AFU Example 6. Compiling the DMA AFU Example 7. Simulating the AFU Example 8. Optimization for Improved DMA Performance 9. DMA Accelerator Functional Unit User Guide Archives 10. Document Revision History for the DMA Accelerator Functional Unit User Guide
1. About this Document x
1.1. Intended Audience 1.2. Conventions 1.3. Acronyms 1.4. Acceleration Glossary
2. DMA AFU Description x
2.1. Introduction 2.2. The DMA AFU Software Package 2.3. The DMA AFU Hardware Components
2.3. The DMA AFU Hardware Components x
2.3.1. DMA Test System 2.3.2. DMA BBB
3. Register Map and Address Spaces x
3.1. DMA AFU Register Map
3.1. DMA AFU Register Map x
3.1.1. DMA AFU Address Space 3.1.2. Device Feature Header Linked-List
1. About this Document
2. DMA AFU Description
3. Register Map and Address Spaces
4. Software Programming Model
5. Running DMA AFU Example
6. Compiling the DMA AFU Example
7. Simulating the AFU Example
8. Optimization for Improved DMA Performance
9. DMA Accelerator Functional Unit User Guide Archives
10. Document Revision History for the DMA Accelerator Functional Unit User Guide

2.3. The DMA AFU Hardware Components

The DMA AFU interfaces with the FPGA Interface Unit (FIU) and FPGA memory.

Refer to the FPGA Interface Manager Data Sheet for Intel FPGA Programmable Acceleration Card D5005 for detailed specifications of the FPGA memory.

Note: The currently available hardware dictates this memory configuration. Future hardware may support different memory configurations.

You can use the DMA AFU to copy data between the following source and destination locations:

  • The host to device FPGA memory
  • Device FPGA memory to the host

A Platform Designer system, $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/hw/rtl/TEST_dma/<device>/dma_test_system.qsys implements most of the DMA AFU.

Part of the DMA AFU implemented in the Platform Designer system can be found in the following location: 
$OPAE_PLATFORM_ROOT/hw/samples/dma_afu/hw/rtl/TEST_dma/<device>
You can find the DMA BBB in the following location: 
$OPAE_PLATFORM_ROOT/hw/samples/dma_afu/hw/rtl/dma_bbb

Figure 1. DMA AFU Hardware Block Diagram

The DMA AFU includes the following internal modules to interface with the FPGA Interface Unit (FIU):

  • Memory-Mapped IO (MMIO) Decoder Logic: detects MMIO read and write transactions and separates them from the CCI-P RX channel 0 that they arrive from. This ensures that MMIO traffic never reaches the MPF BBB and is serviced by an independent MMIO command channel.
  • Memory Properties Factory (MPF): This module ensures that read responses from the DMA return in the order that they were issued. The Avalon® -MM protocol requires read responses to return in the correct order.
  • CCI-P to Avalon® -MM Adapter: This module translates between CCI-P and Avalon® -MM transactions, as follows:
    • CCI-P to Avalon® -MMIO Adapter: This path translates CCI-P MMIO transactions into Avalon® -MM transactions.
    • Avalon® to CCI-P Host Adapter: These paths create separate read-only and write-only paths for the DMA to access host memory.
  • DMA Test System: This module serves as a wrapper around the DMA BBB to expose the DMA masters to the rest of the logic in the AFU. It provides the interface between the DMA BBB and the CCI-P to Avalon® Adapter. It also provides the interface between the DMA BBB and the local FPGA SDRAM banks.

Section Content
DMA Test System
DMA BBB

Related Information
Level Two Title