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2.1. Block-Based Design Terminology
2.2. Block-Based Design Overview
2.3. Design Methodologies Overview
2.4. Design Partitioning
2.5. Design Block Reuse Flows
2.6. Incremental Block-Based Compilation Flow
2.7. Setting-Up Team-Based Designs
2.8. Bottom-Up Design Considerations
2.9. Debugging Block-Based Designs with the Signal Tap Logic Analyzer
2.10. Block-Based Design Flows Revision History
2.11. Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design Document Archive
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2.4.3. Design Partition Guidelines
Creating a design partition creates a logical hierarchical boundary around that instance. This partition boundary can limit the Compiler's ability to merge the partition's logic with other parts of the design. A partition boundary can also prevent optimization that reduces cell and interconnect delay, thereby reducing design performance. To minimize these effects, follow these general design partition guidelines:
- Register partition boundary ports. This practice can reduce unnecessary long delays by confining register-to-register timing paths to a single partition for optimization. This technique also minimizes the effect of the physical placement for boundary logic that the Compiler might place without knowledge of other partitions.
- Minimize the timing-critical paths passing in or out of design partitions. For timing critical-paths that cross partition boundaries, rework the partition boundaries to avoid these paths. Isolate timing-critical logic inside a single partition, so the Compiler can effectively optimize each partition independently.
- Avoid creating a large number of small partitions throughout the design. Excessive partitioning can impact performance by preventing design optimizations.
- Avoid grouping unrelated logic into a large partition. If you are working to optimize an independent block of your design, assigning that block as a small partition provides you more flexibility during optimization.