Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design

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ID 683247
Date 11/07/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Block-Based Design Flows A. Intel® Quartus® Prime Pro Edition User Guides
2. Block-Based Design Flows x
2.1. Block-Based Design Terminology 2.2. Block-Based Design Overview 2.3. Design Methodologies Overview 2.4. Design Partitioning 2.5. Design Block Reuse Flows 2.6. Incremental Block-Based Compilation Flow 2.7. Setting-Up Team-Based Designs 2.8. Bottom-Up Design Considerations 2.9. Debugging Block-Based Designs with the Signal Tap Logic Analyzer 2.10. Block-Based Design Flows Revision History 2.11. Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design Document Archive
2.2. Block-Based Design Overview x
2.2.1. Design Block Reuse Overview 2.2.2. Incremental Block-Based Compilation Overview
2.2.1. Design Block Reuse Overview x
2.2.1.1. Design Block Reuse Examples
2.3. Design Methodologies Overview x
2.3.1. Top-Down Design Methodology Overview 2.3.2. Bottom-Up Design Methodology Overview 2.3.3. Team-Based Design Methodology Overview
2.4. Design Partitioning x
2.4.1. Planning Partitions for Periphery IP, Clocks, and PLLs 2.4.2. Creating Design Partitions 2.4.3. Design Partition Guidelines
2.5. Design Block Reuse Flows x
2.5.1. Reusing Core Partitions 2.5.2. Reusing Root Partitions 2.5.3. Reserved Core Entity Re-Binding 2.5.4. Viewing Quartus Database File Information
2.5.1. Reusing Core Partitions x
2.5.1.1. Step 1: Developer: Create a Design Partition 2.5.1.2. Step 2: Developer: Compile and Export the Core Partition 2.5.1.3. Step 3: Developer: Create a Black Box File 2.5.1.4. Step 4: Consumer: Add the Core Partition and Compile
2.5.2. Reusing Root Partitions x
2.5.2.1. Step 1: Developer: Create a Reserved Core Partition 2.5.2.2. Step 2: Developer: Define a Logic Lock Region 2.5.2.3. Step 3: Developer: Compile and Export the Root Partition 2.5.2.4. Step 4: Consumer: Add the Root Partition and Compile
2.5.4. Viewing Quartus Database File Information x
2.5.4.1. QDB File Attribute Types
2.6. Incremental Block-Based Compilation Flow x
2.6.1. Design Abstraction
2.6.1. Design Abstraction x
2.6.1.1. Empty Partition Clock Source Preservation
2.7. Setting-Up Team-Based Designs x
2.7.1. Creating a Top-Level Project for a Team-Based Design
2.7.1. Creating a Top-Level Project for a Team-Based Design x
2.7.1.1. Prepare a Design Partition for Project Integration
1. Answers to Top FAQs
2. Block-Based Design Flows
A. Intel® Quartus® Prime Pro Edition User Guides

2.1. Block-Based Design Terminology

This document refers to the following terms to explain block-based design methods:

Table 1.  Block-Based Design Terminology
Term Description
Black Box File RTL source file that contains only port and module or entity definitions, without any logic. Include parameters or generics passed to the module or entity to ensure that the configuration matches the implementation in the Consumer project.

Block

Logic that comprises a hierarchical design instance, typically represented by a Verilog module or VHDL entity. You designate a design block as a design partition to empty or export the block.
Consumer A Consumer can reuse a design partition that a Developer exports as a Partition Database File (.qdb) from another project.
Core Partition A design partition that contains only FPGA resources for the implementation of core logic, such as LUTs, registers, M20K memory blocks, and DSPs. A core partition cannot include periphery resources.

Design Partition

A logical, named, hierarchical boundary assignment that you can apply to a design instance. Creating a partition creates a logical boundary and prevents logic optimization and merging with parent or child partitions. Design partitions facilitate incremental block-based compilation and design block reuse by logically separating instances.

Developer A Developer creates and exports a design partition as a .qdb for use in a Consumer project.

Floorplanning

Planning the physical layout of FPGA device resources. The manual process of assigning the logical design hierarchy and periphery to physical regions in the device and I/O.

Logic Lock Region Constraints

Constrains the placement and routing of logic to a specific region in the target device. Specify the region origin, height, width, and any of the following options:
  • Reserved—prevents the Fitter from placing non-member logic within the region.
  • Core-Only—applies the constraint only to core logic in the region, and does not include periphery logic in the region.
  • Routing Region—restricts the routing of connections between region members to the specified area. The routing region is non-exclusive. Other resources in the parent or sibling hierarchy levels can use that routing area. You can restrict the routing region to areas equal to or larger than the Logic Lock region, up to the entire chip. The default routing region is the entire chip.
  • Size/State—fixes the size and locks the state of the region. The Fixed/Locked option defines a region of fixed size and locked location. The Auto/Floating option defines a region with a floating location that automatically sizes to the logic.

Project

The Intel® Quartus® Prime software organizes the source files, settings, and constraints within a project of one or more revisions. The Intel® Quartus® Prime Project File (.qpf) stores the project name and references each project revision that you create.

Root Partition

The Intel® Quartus® Prime software automatically creates a top-level "root_partition" with a hierarchy path of |for each project revision. The root partition includes all device periphery resources (such as I/O, HSSIO, memory interfaces, and PCIe*) and associated core resources. You can export and reuse periphery resources by exporting the root partition and reserving a region for subsequent development (the reserved core) by a Consumer.

Snapshot

A snapshot is a view of the design after a compilation stage. The Intel® Quartus® Prime Compiler generates a snapshot of the compilation database after each compilation stage. You can export a specific snapshot for incremental block-based compilation, design block reuse, and team based designs.

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