Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 4/01/2024
Public
Document Table of Contents

2.3.5.1.1. Targeting Constraints to Module Inputs and Outputs

SDC-on-RTL allows you to define constraints at module boundaries, even if some internal connections within the modules or IP remain partially unknown. It is best to apply SDC-on-RTL constraints at the module boundaries, specifically at the input and output boundaries of each module.

When targeting your timing constraints to the inputs and outputs of a module, you can target the following different element types, depending on your circumstances:

inst_port—these elements are retrieved in collections due to applying the get_pins filter. They target inputs and outputs of modules in a manner similar to addressing pins on registers and LUTs.
# inside 
get_pins {clk_in} clk_dic.rtlsdc
Note: Use get_pins for constraints that expect pins as targets.
Figure 61. Targeting the Instance Port


port— these elements reside within the module and are primarily for use in targeting ports in entity-bound constraints. You can employ the get_ports filter for this purpose.
# Inside
get_ports {clk_in} clk_dic.rtlsdc
Note: Use get_ports for constraints that expect ports as targets.
Figure 62. Targeting the Port