Visible to Intel only — GUID: mwh1410383722386
Ixiasoft
Visible to Intel only — GUID: mwh1410383722386
Ixiasoft
2.4.1.1.1. Automatic Clock Detection and Constraint Creation
The following command specifies a base clock with a 100 MHz requirement for unconstrained base clock nodes.
derive_clocks -period 10
The derive_clocks command names the automatically created base clocks according to the name of the register or port that is the target of each clock. Automatically derived clocks have the suffix “~derived". You can choose another suffix to append with the -suffix option for the derive_clocks command.
If you want to create some base clocks automatically, use the -create_base_clocks option to derive_pll_clocks. With this option, the derive_pll_clocks command automatically creates base clocks for each PLL, based on the input frequency information that you specify when you generate the PLL. This feature works for simple port-to-PLL connections. Base clocks do not automatically generate for complex PLL connectivity, such as cascaded PLLs. You can also use the command derive_pll_clocks -create_base_clocks to create the input clocks for all PLL inputs automatically.