Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 1/31/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.6. Applying Timing Constraints

The following section describes correct application of SDC timing constraints that guide design synthesis, Fitter placement, and produce accurate timing analysis. You can create an .sdc file with a set of initial recommended constraints, and then iteratively modify those constraints as the design progresses.