Visible to Intel only — GUID: vgo1440130911071
Ixiasoft
Visible to Intel only — GUID: vgo1440130911071
Ixiasoft
2.4. Asynchronous Clear and Synchronous Clear
For the asynchronous clear (aclr) signal, the RAM outputs are cleared immediately when the aclr signal asserts. The outputs stay cleared until the next read cycle after the aclr signal de-asserts.
For the synchronous clear (sclr) signal, the RAM outputs are cleared at the next rising edge of the output clock when the (sclr) signal is asserted. The outputs stay cleared until the next read cycle after the sclr signal de-asserts.