3.3. O-RAN Reset Transactions
The five external reset ports are:
- rst_tx_n. Resets the O-RAN IP in the transmission direction. Resets the common header mapper, transmission window monitor and C and U-plane mapper.
- rst_rx_n. Resets the O-RAN IP in the receiver direction. Resets the common header demapper, reception window monitor and C- and U-plane demapper.
- rst_csr_n. Resets the O-RAN IP control and status registers. Assert to reset the IP.
- tx_lanes_stable. Resets the O-RAN IP in the transmission direction when deasserted. Assertion indicates the transmitter clock is stable and O-RAN IP transmitter path is ready to come out from reset. Connect this reset to the Ethernet MAC output or tie to 1.
- rx_pcs_ready. Resets the O-RAN IP in the receiver direction when deasserted. Assertion indicates the receiver clock is stable and O-RAN IP receiver path is ready to come out from reset. Connect this reset to the Ethernet MAC output or tie to 1.
Intel expects the three external reset ports to assert together to fully reset the O-RAN IP. You can deassert the three reset ports together or deassert rst_csr_n, then rst_tx_n, and rst_rx_n to reset CSR, transmitter path, receiver path, respectively.
You must assert rst_tx_n and rst_rx_n to reset the transmitter path and receiver path after reconfiguring functional_mode or static_udcomphdr registers through CSR interface.
The reset flow occurs before the O-RAN IP starts. Deassert the Avalon Streaming application interface ready signals to indicate IP is not ready to receive any transaction.
Alternatively, you can trigger a reset after reconfiguring O-RAN IP during run time.