O-RAN Intel® FPGA IP User Guide

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ID 683238
Date 11/03/2021
Public

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Document Table of Contents
Document Table of Contents x
1. About the O-RAN Intel® FPGA IP 2. Getting Started with the O-RAN Intel® FPGA IP 3. O-RAN IP Functional Description 4. O-RAN IP Registers 5. O-RAN Intel FPGA IPs User Guide Archive 6. Document Revision History for the O-RAN Intel® FPGA IP User Guide
1. About the O-RAN Intel® FPGA IP x
1.1. O-RAN Intel® FPGA IP Features 1.2. O-RAN Intel® FPGA IP Device Family Support 1.3. Release Information for the O-RAN Intel® FPGA IP 1.4. O-RAN Intel® FPGA IP Performance and Resource Utilization
2. Getting Started with the O-RAN Intel® FPGA IP x
2.1. Obtaining, Installing, and Licensing the O-RAN IP 2.2. Parameterizing the O-RAN IP 2.3. Generated IP File Structure
2.2. Parameterizing the O-RAN IP x
2.2.1. O-RAN IP Parameters
3. O-RAN IP Functional Description x
3.1. O-RAN IP Signals 3.2. O-RAN Intel® FPGA IP Error Handling 3.3. O-RAN Reset Transactions 3.4. O-RAN IP Streaming Mode 3.5. O-RAN IP Performance Counters 3.6. O-RAN IP Transmission and Reception Window Threshold
1. About the O-RAN Intel® FPGA IP
2. Getting Started with the O-RAN Intel® FPGA IP
3. O-RAN IP Functional Description
4. O-RAN IP Registers
5. O-RAN Intel FPGA IPs User Guide Archive
6. Document Revision History for the O-RAN Intel® FPGA IP User Guide

1.1. O-RAN Intel® FPGA IP Features

  • Support for CAT-A RU (up to 8 spatial streams)
  • Support for CAT-B RU (precoding in RU)
  • Support for section extensions from 1 to 11
  • Bandwidth saving:
    • Programmable static bit-width fixed-point IQ
    • Real-time variable bit-width
    • Compressed IQ
    • Block floating-point compression
    • μ-law compression
    • Variable bit-width per channel (per data section)
    • Static configuration of U-plane IQ format and compression header
  • Transmission blanking energy savings
  • Preconfigured transport delay method CU–RU timing
  • Section type 0, type 1, and type 3
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