O-RAN Intel® FPGA IP User Guide

ID 683238
Date 11/03/2021
Public

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6. Document Revision History for the O-RAN Intel® FPGA IP User Guide

Date IP Version Intel® Quartus® Prime Software Version Changes
2021.11.03 1.5.1 21.2
  • Corrected Reception Window figure
2021.09.15 1.5.1 21.2
  • Corrected readyLatency in Receiver Signals table
2021.08.11 1.4.0 21.1
  • Corrected csr_read in CSR Signals table
2021.06.17 1.4.0 21.1
  • Corrected readyLatency in Transmitter Signals table
2021.06.10 1.4.0 21.1
  • Added support for F-tile devices
  • Moved rx_sec_hdr_valid signal from control plane to user plane table
2021.04.22 1.3.0 20.4
  • Added more signals to C-plane packet waveform
  • Updated tx_total_low, tx_total_high, tx_total_c_low, and tx_total_c_high register addresses
2021.03.20 1.3.0 20.4 Added:
  • New registers.
  • Performance Counters
  • O-RAN IP Transmission and Reception Window Threshold
  • Support for section extensions.
  • Compression ratios of 8, 9, 10, 11, 12, 13, 14, 15, 16.
  • Section type 3
2021.01.25 1.0.0 20.2
  • Changed product ordering code.
2020.09.04 1.0.0 20.2 Initial release.