Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

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Date 6/26/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Design Compilation 3. Reducing Compilation Time 4. Intel® Quartus® Prime Pro Edition User Guide Design Compilation Archives A. Intel® Quartus® Prime Pro Edition User Guides
2. Design Compilation x
2.1. Compilation Overview 2.2. Using the Compilation Dashboard 2.3. Design Netlist Infrastructure (Beta) 2.4. Design Synthesis 2.5. Design Place and Route 2.6. Incremental Optimization Flow 2.7. Fast Forward Compilation Flow 2.8. Full Compilation Flow 2.9. Exporting Compilation Results 2.10. Integrating Other EDA Tools 2.11. Synthesis Language Support 2.12. Compiler Optimization Techniques 2.13. Synthesis Settings Reference 2.14. Fitter Settings Reference 2.15. Design Compilation Revision History
2.1. Compilation Overview x
2.1.1. Compilation Flows 2.1.2. Compilation Hierarchy 2.1.3. Compilation Monitoring
2.3. Design Netlist Infrastructure (Beta) x
2.3.1. Exploring the RTL Analyzer (Beta) 2.3.2. Early Timing Analysis After Design Synthesis (Beta) 2.3.3. DNI Use Case Examples
2.3.1. Exploring the RTL Analyzer (Beta) x
2.3.1.1. Sweep Hints Viewer 2.3.1.2. Connectivity Tracer 2.3.1.3. Object Set Console 2.3.1.4. Module Interfaces 2.3.1.5. Bundled Instances 2.3.1.6. Auto-hide Unconnected Pins 2.3.1.7. Filtering Ports and Nets 2.3.1.8. Expand Connections
2.3.2. Early Timing Analysis After Design Synthesis (Beta) x
2.3.2.1. Synopsys* Design Constraint (SDC) on RTL 2.3.2.2. Post-Synthesis Static Timing Analysis (STA) 2.3.2.3. Types of SDC Files Used in the Intel® Quartus® Prime Software
2.3.2.1. Synopsys* Design Constraint (SDC) on RTL x
2.3.2.1.1. Registering the SDC-on-RTL SDC File 2.3.2.1.2. Applying the SDC-on-RTL Constraints 2.3.2.1.3. Inspecting SDC-on-RTL Constraints 2.3.2.1.4. Creating Constraints in SDC-on-RTL SDC Files SDC 2.1 Compliance Identifying Timing Paths Debugging SDC-on-RTL Constraints
2.3.3. DNI Use Case Examples x
2.3.3.1. Scripting Routine Tasks Using DNI Tcl Commands 2.3.3.2. Traversing the DNI Netlist Using Tcl Commands
2.4. Design Synthesis x
2.4.1. Running Synthesis 2.4.2. Viewing Synthesis Reports 2.4.3. Viewing Synthesis Dynamic Report
2.4.1. Running Synthesis x
2.4.1.1. Preserving Registers During Synthesis 2.4.1.2. Preserving Signals for Monitoring and Debugging
2.5. Design Place and Route x
2.5.1. Running the Fitter 2.5.2. Viewing Fitter Reports
2.5.1. Running the Fitter x
2.5.1.1. Fitter Commands 2.5.1.2. Disabling or Enabling Physical Synthesis Optimization
2.5.2. Viewing Fitter Reports x
2.5.2.1. Plan Stage Reports 2.5.2.2. Place Stage Reports 2.5.2.3. Route Stage Reports 2.5.2.4. Retime Stage Reports 2.5.2.5. Finalize Stage Reports
2.5.2.2. Place Stage Reports x
2.5.2.2.1. Global Signal Visualization Report
2.5.2.3. Route Stage Reports x
2.5.2.3.1. Global Router Congestion Hotspot Summary Report 2.5.2.3.2. Global Router Wire Utilization Map Report
2.6. Incremental Optimization Flow x
2.6.1. Concurrent Analysis During Synthesis or Fitting 2.6.2. Analyzing Compiler Snapshots 2.6.3. Validating Periphery (I/O) after the Plan Stage
2.6.2. Analyzing Compiler Snapshots x
2.6.2.1. Running Snapshot Viewer
2.6.2.1. Running Snapshot Viewer x
2.6.2.1.1. Analyzing Failing Paths with Snapshot Viewer 2.6.2.1.2. Analyzing Clocking with Snapshot Viewer 2.6.2.1.3. Analyzing High Fan-out Nets with Snapshot Viewer 2.6.2.1.4. Validating Timing Constraints with Snapshot Viewer 2.6.2.1.5. Analyzing Congestion with Snapshot Viewer
2.7. Fast Forward Compilation Flow x
2.7.1. Step 1: Run Register Retiming 2.7.2. Step 2: Review Retiming Results 2.7.3. Step 3: Run Fast Forward Compile 2.7.4. Step 4: Review Fast Forward Results 2.7.5. Step 5: Implement Fast Forward Recommendations 2.7.6. Retiming Restrictions and Workarounds
2.7.2. Step 2: Review Retiming Results x
2.7.2.1. Locate Critical Chains
2.7.3. Step 3: Run Fast Forward Compile x
2.7.3.1. Fast Forward Compile By Hierarchy 2.7.3.2. HyperFlex Settings
2.7.4. Step 4: Review Fast Forward Results x
2.7.4.1. Clock Fmax Summary Report 2.7.4.2. Fast Forward Details Report
2.8. Full Compilation Flow x
2.8.1. Full Compilation Flow with Temporary Optimization Mode
2.9. Exporting Compilation Results x
2.9.1. Exporting a Version-Compatible Compilation Database 2.9.2. Importing a Version-Compatible Compilation Database 2.9.3. Creating a Design Partition 2.9.4. Exporting a Design Partition 2.9.5. Reusing a Design Partition 2.9.6. Viewing Quartus Database File Information 2.9.7. Clearing Compilation Results
2.9.6. Viewing Quartus Database File Information x
2.9.6.1. QDB File Attribute Types
2.10. Integrating Other EDA Tools x
2.10.1. Generating a VQM Netlist for other EDA Tools
2.11. Synthesis Language Support x
2.11.1. Verilog and SystemVerilog Synthesis Support 2.11.2. VHDL Synthesis Support
2.11.1. Verilog and SystemVerilog Synthesis Support x
2.11.1.1. Verilog HDL Input Settings (Settings Dialog Box) 2.11.1.2. Design Libraries 2.11.1.3. Verilog HDL Configuration 2.11.1.4. Initial Constructs and Memory System Tasks 2.11.1.5. Verilog HDL Macros
2.11.1.3. Verilog HDL Configuration x
2.11.1.3.1. Hierarchical Design Configurations
2.11.2. VHDL Synthesis Support x
2.11.2.1. VHDL Input Settings (Settings Dialog Box) 2.11.2.2. VHDL Standard Libraries and Packages 2.11.2.3. VHDL wait Constructs 2.11.2.4. VHDL-2019 Conditional Analysis Tool Directives
2.12. Compiler Optimization Techniques x
2.12.1. Compiler Optimization Modes 2.12.2. Allow Register Retiming 2.12.3. Automatic Gated Clock Conversion 2.12.4. Enable Intermediate Fitter Snapshots 2.12.5. Fast Preserve Option 2.12.6. Fractal Synthesis Optimization
2.12.6. Fractal Synthesis Optimization x
2.12.6.1. Enabling or Disabling Fractal Synthesis
2.13. Synthesis Settings Reference x
2.13.1. Advanced Synthesis Settings
3. Reducing Compilation Time x
3.1. Factors Affecting Compilation Results 3.2. Strategies to Reduce the Overall Compilation Time 3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time 3.4. Reducing Placement Time 3.5. Reducing Routing Time 3.6. Reducing Static Timing Analysis Time 3.7. Setting Process Priority 3.8. Reducing Compilation Time Revision History
3.2. Strategies to Reduce the Overall Compilation Time x
3.2.1. Running the ECO Compilation Flow 3.2.2. Enabling Multi-Processor Compilation 3.2.3. Using Block-Based Compilation
3.2.2. Enabling Multi-Processor Compilation x
3.2.2.1. Processor Base Clock Frequency 3.2.2.2. Random Access Memory (RAM) 3.2.2.3. Storage
3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time x
3.3.1. Settings to Reduce Synthesis Time and Synthesis Netlist Optimization Time 3.3.2. Use Appropriate Coding Style to Reduce Synthesis Time
3.4. Reducing Placement Time x
3.4.1. Placement Effort Multiplier Settings
3.5. Reducing Routing Time x
3.5.1. Identifying Routing Congestion with the Chip Planner
3.5.1. Identifying Routing Congestion with the Chip Planner x
3.5.1.1. Areas with Routing Congestion 3.5.1.2. Congestion due to HDL Coding style
1. Answers to Top FAQs
2. Design Compilation
3. Reducing Compilation Time
4. Intel® Quartus® Prime Pro Edition User Guide Design Compilation Archives
A. Intel® Quartus® Prime Pro Edition User Guides

2.3.2.1.4. Creating Constraints in SDC-on-RTL SDC Files

SDC 2.1 Compliance

SDC-on-RTL SDCs is an industry-standard to provide constraints targeting your RTL. Target nodes are from the elaborated netlist and aligned closely with your RTL. You can target hierarchical nodes and propagate constraints into the compilation flow through various compilation stages.

Note: The read_sdc command loads SDC-on-RTL SDC files into the Timing Analyzer. Depending on the snapshot you loaded, read_sdc attempts to read other SDCs suitable for that snapshot. For additional information about the types of SDC files used for different use cases, refer to Types of SDC Files Used in the Intel® Quartus® Prime Software.

The Intel® Quartus® Prime software preserves the order of constraints in SDC-on-RTL SDC files. The order in which you list constraints in the SDC file defines the order in which they are loaded in the Intel® Quartus® Prime software.

SDC-on-RTL constraints are designed to support only SDC 2.1-compliant commands. Object accessors, such as get_keepers, get_registers, or get_nodes, are notably absent. The following is the list of supported SDC commands, and you can find more information about them in the TCL Commands and Packages Summary section of the Intel® Quartus® Prime Pro Edition User Guide: Scripting:

  • create_clock
  • create_generated_clock
  • set_input_delay
  • set_output_delay
  • set_false_path
  • set_max_delay
  • set_min_delay
  • set_multicycle_path
  • set_clock_groups
  • set_clock_latency
  • set_clock_uncertainty
  • set_data_delay
  • set_net_delay
  • set_max_skew
Note: Not all of these commands support the full selection of SDC 2.1 arguments because the Timing Analyzer does not support all arguments. If you specify an unsupported argument, these commands issue a warning message and ignore the argument. If you prefer a Tcl error when you encounter a warning in the Timing Analyzer, set the ERROR_ON_WARNINGS_LOADING_SDC_ON_RTL_CONSTRAINTS QSF variable to ON.

Identifying Timing Paths

For defining timing paths, use SDC standard accessors, such as get_pins, instead of the Intel® Quartus® Prime software-specific commands, such as get_keepers or get_registers. Intel® recommends using explicit get_<pins|ports|nets> commands when targeting objects. Using bare names can result in unintended targets, and DNI might issue a warning.

Intel® Quartus® Prime Conventional SDC (targets Intel® Quartus® Prime timing graph): 
set_false_path -from [get_keepers { reg_A }] -to [get_keepers { reg_B }]
SDC-on-RTL SDC (targets your netlist nodes): 
set_false_path -from [get_pins { reg_A|clk }] -to [get_pins { reg_B|d }]
Note: The path must start at the register clk pin to identify the timing path. If your design uses reg_A|d or reg_A|q, the timing path in the Timing Analyzer is invalid, as shown in the Report Exception report:
Status Exception Command From Flag From To Flag To Setup Slack
Complete set_false_path -from

[get_pins{tf_sync[0] |ff_src|clk}]

-to

[get_pins{tf_sync[0] |ff_dst|d}]

3.603
Invalid set_false_path -from

[get_pins{tf_sync[2] |ff_src|q}]

-to

[get_pins{tf_sync[2] |ff_dst|d}]

Invalid
Invalid set_false_path -from

[get_pins{tf_sync[3] |ff_src|d}]

-to

[get_pins{tf_sync[3] |ff_dst|d}]

Invalid
Note: Netlist targets are case-sensitive. Sometimes, the lower-level module ports are capitalized. In this case, using the -nocase option with the get_<pins|ports|nets> commands ignore the case sensitivity.

Debugging SDC-on-RTL Constraints

There are several ways to debug SDC-on-RTL constraints. For example, you can isolate the exact locations where constraints are used in your design and analyze them in the flow. You can also use compilation reports that report the constraints (see Post-Elaboration Constraints Compilation Report). However, when debugging the constraints, consider the following:

Explicit Errors When Loading Constraints

Errors with reading SDC-on-RTL constraints issue an error message with a command stack showing the line number of the offending command. For example:

You can debug erroneous constraints directly through the DNI Tcl console. You can iterate on issues with initial target resolution or command syntax at this early stage easily, as this is the stage where Intel® Quartus® Prime software loads the SDC-on-RTL SDC files.

Note:

In general, it is not possible to directly load SDC-on-RTL constraints in the Timing Analyzer because of the following reasons:

  • The target netlist is different in the elaborated netlist and not the timing netlist. Although there may be some common nodes between the two netlists, both netlists are different.
  • Compliant SDC 2.1 syntax used in SDC-on-RTL can be different from the conventional Quartus SDC commands.

Constraint Behavior and Interpretation Issues

When handling the constraints, ensure the following:

  • Targets and basic syntax are correct (node finding or target acquisition). You can use the RTL Analyzer to find the nodes on the elaborated netlist.
  • Constraints make sense with respect to the timing graph (constraint behavior). You can review this in the Timing Analyzer.

    Examine the SDC-on-RTL constraints conveyed to the Timing Analyzer (import_sdc loads only the SDC-on-RTL commands) from the design netlist. The import_sdc command loads a version of the SDC-on-RTL constraints after propagating through various stages of the compile flow. After this step, the experience is the same as a typical Timing Analyzer session.

Note: Although Intel® does not recommend loading raw SDC-on-RTL SDC files from the Timing Analyzer, you can issue Timing Analyzer-compatible SDC commands using the Timing Analyzer Tcl console to debug your design. By issuing SDC commands directly, you can override SDC-on-RTL constraints and explore the effect of changing the values. However, the changes are valid only for that timing analysis session. For permanent changes, you must update the source SDC-on-RTL SDC file and rerun Analysis and Elaboration.
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