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1. About the O-RAN Intel® FPGA IP Design Example
2. Getting Started with the O-RAN Intel® FPGA IP Design Example
3. O-RAN Intel® FPGA IP Design Example Functional Description
4. O-RAN IP Design Example User Guide Archives
5. Document Revision History for the O-RAN Intel® FPGA IP Design Example User Guide
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2.2.1. Simulating the O-RAN Design Example for Agilex™ 7 F-Tile Devices
When targeting Agilex™ 7 F-tile devices, the design example supports VCS, Questa, and Xcelium simulations only.
- Turn on Example Design > Files Types Generated > Simulation.
- Change the directory to <simulation design example> /simulation/quartus.
- Run these two commands:
quartus_ipgenerate --run_default_mode_op oran_ed -c oran_edquartus_tlg oran_ed..
- Change the directory to <simulation design example> /simulation/setup_scripts.
- Run this command: ip-setup-simulation --quartus-project=../quartus/oran_ed.qpf.
- For VCS:
- Change the directory to <simulation design example> /simulation/setup_scripts/synopsys/vcs.
- Run this command: sh run_vcs.sh.
- For Questa:
- Change the directory to <simulation design example>/simulation/setup_scripts/mentor
- Run this script in the Questa simulator: do run_vsim.do.
- For Xcelium:
- Change the directory to <simulation design example>/simulation/setup_scripts/xcelium
- Run this command: sh run_xcelium.sh