O-RAN Intel® FPGA IP Design Example User Guide

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ID 683218
Date 11/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the O-RAN Intel® FPGA IP Design Example 2. Getting Started with the O-RAN Intel® FPGA IP Design Example 3. O-RAN Intel® FPGA IP Design Example Functional Description 4. O-RAN IP Design Example User Guide Archives 5. Document Revision History for the O-RAN Intel® FPGA IP Design Example User Guide
2. Getting Started with the O-RAN Intel® FPGA IP Design Example x
2.1. Generating the O-RAN IP Design Example 2.2. Simulating the O-RAN IP Design Example 2.3. Operating the O-RAN IP Design Example
2.1. Generating the O-RAN IP Design Example x
2.1.1. O-RAN IP Design Example Parameters
2.2. Simulating the O-RAN IP Design Example x
2.2.1. Simulating the O-RAN Design Example for Agilex™ 7 F-Tile Devices 2.2.2. Enabling Dynamic Reconfiguation to the Ethernet IP 2.2.3. O-RAN IP Design Example Testbench
2.3. Operating the O-RAN IP Design Example x
2.3.1. Generating and Downloading the Linking Format .elf Programming File
1. About the O-RAN Intel® FPGA IP Design Example
2. Getting Started with the O-RAN Intel® FPGA IP Design Example
3. O-RAN Intel® FPGA IP Design Example Functional Description
4. O-RAN IP Design Example User Guide Archives
5. Document Revision History for the O-RAN Intel® FPGA IP Design Example User Guide

1. About the O-RAN Intel® FPGA IP Design Example

Updated for:
Intel® Quartus® Prime Design Suite 24.3
IP Version 3.1.0
The design example allows you to simulate, compile, and test your O-RAN IP instance on various development boards. The design example includes Ethernet IP, eCPRI IP, eCPRI IOPLL, PTP IOPLL, and a test wrapper.

The compiled hardware design example runs on the:

  • Agilex™ 5 FPGA E-Series 065B Premium Development Kit
  • Agilex™ 7 F-Series Transceiver-SoC Development Kit for the E-tile design examples
  • Agilex™ 7 I-Series Transceiver-SoC Development Kit
  • Arria® 10 GX Signal Integrity Development Kit
  • Stratix® 10 GX Transceiver Signal Integrity Development Kit for the H-tile design examples
  • Stratix® 10 TX Transceiver Signal Integrity Development Kit for the E-tile design examples

In Agilex 5 devices, the design example does not support multichannel configuration. The design supports 10G or 25G Ethernet data rate depending on the device. For more information, refer to GTS Ethernet Hard IP Design Example User Guide. The design does not support dynamic reconfiguration between 25G and 10G Ethernet data rate.

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