External Memory Interfaces Agilex™ 7 F-Series and I-Series FPGA IP User Guide

ID 683216
Date 9/19/2024
Public
Document Table of Contents

4.1.2.12. emif_usr_reset_n for QDR-IV

User clock domain reset interface
Table 51.  Interface: emif_usr_reset_nInterface type: Reset Output
Port Name Direction Description
emif_usr_reset_n Output Reset for the user clock domain. Asynchronous assertion and synchronous deassertion