The following file and directories define the AFU simulation:

• $OPAE_PLATFORM_ROOT/hw/samples/<AFU example> /hw/rtl/filelist.txt specifies RTL sources.
• <AFU example> is the example directory as shown in the hello_afu Directory Tree figure.
• filelist.txt lists SystemVerilog, VHDL, and the AFU JavaScript Object Notation (.json) file.
• The AFU .json describes the interfaces the AFU requires. It also includes a UUID to identify the AFU once downloaded to an FPGA.
• hw/rtl/hello_afu.json defines ccip_std_afu as the top-level interface by setting afu-top-interface to ccip_std_afu. ccip_std_afu is the base CCI-P interface including clocks, reset, and CCI-P TX and RX structures. More advanced examples define other interface options.
• The .json file declares the AFU UUID. An OPAE script generates the UUID. The RTL loads the UUID from afu_json_info.vh.
• sw/Makefile generates afu_json_info.h. Software loads the UUID from afu_json_info.h.