Intel® Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization

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ID 683174
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Power Analysis 3. Power Optimization 4. Power Analysis and Optimization Document Archive A. Intel® Quartus® Prime Pro Edition User Guides
2. Power Analysis x
2.1. Power Analysis Tools 2.2. Running the Power Analyzer 2.3. Specifying Power Analyzer Input 2.4. Viewing Power Analysis Reports 2.5. Power Analysis in Modular Design Flows 2.6. Scripting Support 2.7. Power Analysis Revision History
2.3. Specifying Power Analyzer Input x
2.3.1. Settings for Power Analysis 2.3.2. Specifying Signal Activity Data 2.3.3. Specifying the Default Toggle Rate 2.3.4. Specifying Toggle Rates for Specific Nodes 2.3.5. Avoiding Simulation Node Name Match
2.3.2. Specifying Signal Activity Data x
2.3.2.1. Using Simulation Signal Activity Data in Power Analysis 2.3.2.2. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation 2.3.2.3. Signal Activities from Vectorless Estimation and User-Supplied Input Pin Activities 2.3.2.4. Signal Activities from User Defaults Only
2.3.2.1. Using Simulation Signal Activity Data in Power Analysis x
2.3.2.1.1. Generating Signal Activity Data for Power Analysis 2.3.2.1.2. Generating Standard Delay Output for Power Analysis 2.3.2.1.3. Simulation Glitch Filtering
2.3.2.2. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation x
2.3.2.2.1. RTL Simulation Limitation
2.3.4. Specifying Toggle Rates for Specific Nodes x
2.3.4.1. Clock Node Toggle Rates
2.5. Power Analysis in Modular Design Flows x
2.5.1. Complete Design Simulation Power Analysis Flow 2.5.2. Modular Design Simulation Power Analysis Flow 2.5.3. Multiple Simulation Power Analysis Flow 2.5.4. Overlapping Simulation Power Analysis Flow 2.5.5. Partial Design Simulation Power Analysis Flow 2.5.6. Vectorless Estimation Power Analysis Flow
2.5.5. Partial Design Simulation Power Analysis Flow x
2.5.5.1. Specifying Start and End Time for Signal Activity Calculations
2.6. Scripting Support x
2.6.1. Running the Power Analyzer from the Command–Line
3. Power Optimization x
3.1. Factors Affecting Power Consumption 3.2. Design Space Explorer II for Power-Driven Optimization 3.3. Power-Driven Compilation 3.4. Design Guidelines 3.5. Power Optimization Advisor 3.6. Power Optimization Revision History
3.1. Factors Affecting Power Consumption x
3.1.1. Design Activity and Power Analysis 3.1.2. Device Selection 3.1.3. Environmental Conditions 3.1.4. Device Resource Usage 3.1.5. Signal Activity
3.1.4. Device Resource Usage x
3.1.4.1. Number, Type, and Loading of I/O Pins 3.1.4.2. Number and Type of Hard Logic Blocks 3.1.4.3. Number and Type of Global Signals
3.1.5. Signal Activity x
3.1.5.1. Toggle Rate 3.1.5.2. Static Probability
3.3. Power-Driven Compilation x
3.3.1. Power-Driven Synthesis 3.3.2. Power-Driven Fitter 3.3.3. Area-Driven Synthesis 3.3.4. Gate-Level Register Retiming 3.3.5. Intel® Quartus® Prime Compiler Settings 3.3.6. Assignment Editor Options
3.3.1. Power-Driven Synthesis x
3.3.1.1. Memory Block Optimization 3.3.1.2. Power-Aware Logic Mapping 3.3.1.3. Power-Aware Memory Balancing
3.4. Design Guidelines x
3.4.1. Clock Power Management 3.4.2. Pipelining and Retiming 3.4.3. Architectural Optimization 3.4.4. I/O Power Guidelines 3.4.5. Dynamically Controlled On-Chip Terminations (OCT) 3.4.6. Memory Optimization (M20K/MLAB) 3.4.7. DDR Memory Controller Settings 3.4.8. DSP Implementation 3.4.9. Reducing High-Speed Tile (HST) Usage 3.4.10. Unused Transceiver Channels 3.4.11. Periphery Power reduction XCVR Settings
3.4.1. Clock Power Management x
3.4.1.1. Clock Gating 3.4.1.2. Clock Enable in Memory Blocks 3.4.1.3. LAB Clock Power 3.4.1.4. Clock Enables 3.4.1.5. Global Signals 3.4.1.6. Merge Clocks
3.4.1.1. Clock Gating x
3.4.1.1.1. Root Clock Gate 3.4.1.1.2. Sector Clock Gate 3.4.1.1.3. I/O PLL Clock Gate
3.4.1.3. LAB Clock Power x
3.4.1.3.1. LAB-Wide Clock Enable Example
3.4.1.5. Global Signals x
3.4.1.5.1. Viewing Clock Details in the Chip Planner
3.4.6. Memory Optimization (M20K/MLAB) x
3.4.6.1. Implementation 3.4.6.2. Rd/Wr Enables
3.4.11. Periphery Power reduction XCVR Settings x
3.4.11.1. Transceiver Settings 3.4.11.2. I/O Current Strength
3.5. Power Optimization Advisor x
3.5.1. Set Realistic Timing Constraints 3.5.2. Appropriate Device Family 3.5.3. Dynamic Power 3.5.4. Static Power 3.5.5. Appropriate I/O Standards 3.5.6. Use RAM Blocks 3.5.7. Shut Down RAM Blocks 3.5.8. Clock Enables on Logic 3.5.9. Pipeline Logic to Reduce Glitching
3.5.1. Set Realistic Timing Constraints x
3.5.1.1. Find Timing Information
1. Answers to Top FAQs
2. Power Analysis
3. Power Optimization
4. Power Analysis and Optimization Document Archive
A. Intel® Quartus® Prime Pro Edition User Guides

2.7. Power Analysis Revision History

The following revision history applies to this chapter:

Document Version Intel® Quartus® Prime Version Changes
2023.10.02 23.3
  • Updated the section "Thermal Map Visualization" with additional information in Viewing Power Analysis Reports.
  • Updated the Power Analyzer Settings image and relevant description in Settings for Power Analysis.
  • Updated the product family name to "Intel Agilex 7."
2022.12.12 22.4
  • Updated screenshot in Power Analysis topic.
  • Revised description of On-Chip Power Dissipation by Hierarchy report in Viewing Power Analysis Reports topic.
  • Removed Write out Power and Thermal Calculator file option description from Settings for Power Analysis topic. This setting is replaced by Power and Thermal Calculator File Name option.
  • Revised Running the Power Analyzer topic for Power and Thermal Calculator File Name option.
  • Revised Running the Power Analyzer from the Command Line for new GUI option and removal of obsolete commands.
2022.06.22 21.4 In the Power Analysis Tools topic, added statements about Intel® Quartus® Prime Power Analyzer accuracy for Intel® Stratix® 10 and Intel Agilex designs.
2021.12.13 21.4
  • In the Settings for Power Analysis topic, modified a Thermal Settings entry in the Power Analyzer and Thermal Settings table. Specifically, changed Apply Recommended Margin to Apply Additional Margin, and modified the description accordingly.
  • In the Viewing Power Analysis Reports topic, added the Crypto block type to the On-Chip Power Dissipation by Block Type section.
2021.10.04 21.3 Recast the note in the Power Analysis Tools topic for greater clarity.
2021.03.29 21.1
  • In the Power Analysis topic, updated the figure.
  • In the Running the Power Analyzer topic, modified step 3 and removed the figure following step 9.
  • Changed the title of the Device Operating Condition Settings for Power Analysis topic to Settings for Power Analysis, updated the existing figure and added an additional figure, recast the existing table and added an additional table.
  • In the Generating Signal Activity Data for Power Analysis topic, modified step 5 and the figure within step 6.
  • In the Viewing Power Analysis Reports topic, made minor changes to the first paragraph of the Thermal Map Visualization section.
  • In the Running the Power Analyzer from the Command–Line topic, modified the note at the bottom of the topic.
2020.12.07 20.3.0 Added note to the Specifying the Default Toggle Rate topic.
2020.10.05 20.3.0
  • Added mention of gate-level simulation to the Specifying Power Analyzer Input, Specifying Signal Activity Data, Using Simulation Signal Activity Data in Power Analysis, and Complete Design Simulation Power Analysis Flow topics,
  • Added a sentence to the RTL Simulation Limitation and Avoiding Simulation Node Name Match topics.
  • Added a Thermal Map Visualization section to the Viewing Power Analysis Reports topic.
2020.04.13 20.1.0 Added information about the Intel® FPGA Power and Thermal Calculator to the following topics:
  • Power Analysis
  • Power Analysis Tools
  • Running the Power Analyzer from the Command–Line
2019.12.04 19.1.0
  • Removed references to entity-specific toggle rates in "Specifying Toggle Rates for Specific Nodes." Toggle rates must be either global or node specific.
2019.08.02 19.1.0
  • Clarified wording of statements about .vcd files in "Simulation Glitch Filtering" topic.
  • Corrected typo in "Specifying the Default Toggle Rate" topic.
  • Corrected typo in "Running the Power Analyzer from the Command Line" topic.
  • Improved explanation in "Generating Standard Delay Output for Power Analysis" topic.
2019.07.03 19.1.0
  • Corrected broken links to Help.
2019.04.01 19.1.0
  • Described new support for generation of SDO for use in power analysis.
  • Retitled some topic headings for greater clarity.
  • Changed the order of some topics for improved flow of information.
  • Added descriptions of Power Savings Summary and Parallel Compilation power analysis reports.
  • Added new Power Analysis flow diagrams.
2018.09.24 18.1.0
  • General chapter reorganization.
  • Moved Factors Affecting Power Consumption to chapter: Power Optimization.
  • Updated figure: Power Analyzer High-level Flow.
  • Divided topic: Types of Power Analysis into two topics: Power Estimations and Design Requirements and Design Activity and Power Analysis.
  • Updated figure: Power Analysis Tools from Design Concept through Design Implementation and renamed to: Estimation Accuracy for Different Inputs and Power Analysis Tools
  • Removed content referring to device families not supported in Intel Quartus Prime Pro Edition.
2018.06.11 18.0.0
  • In Comparison of the EPE and the Intel Quartus Prime Power Analyzer, updated the data output types that the Power Analyzer supports.
  • In Comparison of the EPE and the Intel Quartus Prime Power Analyzer, added row about estimation of transceiver power for features that you enable only through dynamic reconfiguration.
  • Specified features not supported by the Power Analyzer.
2017.05.08 17.0.0 Removed references to PowerPlay name. Power analysis occurs in the Intel Quartus Prime Power Analyzer.
2016.10.31 16.1.0
  • Implemented Intel rebranding.
  • Removed support for .vcd generation by the Compiler. Generate .vcd files for power estimation in your EDA simulator.
2015.11.02 15.1.0 Changed instances of Quartus II to Intel Quartus Prime.
2014.12.15 14.1.0
  • Removed Signal Activities from Full Post-fit Netlist (Timing) Simulation and Signal Activities from Full Post-fit Netlist (Zero Delay) Simulation sections as these are no longer supported.
  • Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical Synthesis Optimizations to Compiler Settings.
2014.08.18 14.0a10.0 Updated "Current Drawn from Voltage Supplies" to clarify that for SoC devices or for Arria V SoC and Cyclone V SoC devices, there is no standalone ICC_AUX_SHARED current drawn information. The ICC_AUX_SHARED is reported together with ICC_AUX.
November 2012 12.1.0
  • Updated “Types of Power Analyses” on page 8–2, and “Confidence Metric Details” on page 8–23.
  • Added “Importance of .vcd” on page 8–20, and “Avoiding Power Estimation and Hardware Measurement Mismatch” on page 8–24
June 2012 12.0.0
  • Updated “Current Drawn from Voltage Supplies” on page 8–22.
  • Added “Using the HPS Power Calculator” on page 8–7.
November 2011 10.1.1
  • Template update.
  • Minor editorial updates.
December 2010 10.1.0
  • Added links to Quartus II Help, removed redundant material.
  • Moved “Creating PowerPlay EPE Spreadsheets” to page 8–6.
  • Minor edits.
July 2010 10.0.0
  • Removed references to the Quartus II Simulator.
  • Updated Table 8–1 on page 8–6, Table 8–2 on page 8–13, and Table 8–3 on page 8–14.
  • Updated Figure 8–3 on page 8–9, Figure 8–4 on page 8–10, and Figure 8–5 on page 8–12.
November 2009 9.1.0
  • Updated “Creating PowerPlay EPE Spreadsheets” on page 8–6 and “Simulation Results” on page 8–10.
  • Added “Signal Activities from Full Post-fit Netlist (Zero Delay) Simulation” on page 8–19 and “Generating a .vcd from Full Post-fit Netlist (Zero Delay) Simulation” on page 8–21.
  • Minor changes to “Generating a .vcd from ModelSim Software” on page 8–21.
  • Updated Figure 11–8 on page 11–24.
March 2009 9.0.0
  • This chapter was chapter 11 in version 8.1.
  • Removed Figures 11-10, 11-11, 11-13, 11-14, and 11-17 from 8.1 version.
November 2008 8.1.0
  • Updated for the Quartus II software version 8.1.
  • Replaced Figure 11-3.
  • Replaced Figure 11-14.
May 2008 8.0.0
  • Updated Figure 11–5.
  • Updated “Types of Power Analyses” on page 11–5.
  • Updated “Operating Conditions” on page 11–9.
  • Updated “PowerPlay Power Analyzer Compilation Report” on page 11–31.
  • Updated “Current Drawn from Voltage Supplies” on page 11–32.
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