Embedded Peripherals IP User Guide

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ID 683130
Date 12/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. HPS GMII to RGMII Adapter Intel® FPGA IP 51. Intel FPGA MII to RMII Converter Core 52. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 53. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 54. Intel FPGA MSI to GIC Generator Core 55. Cache Coherency Translator Intel® FPGA IP 56. Altera ACE5-Lite Cache Coherency Translator Intel® FPGA IP 57. Lightweight UART Core
1. Introduction x
1.1. Tool Support 1.2. Device Support 1.3. Embedded Peripherals IP User Guide Archives 1.4. Document Revision History for Embedded Peripherals IP User Guide
2. Avalon® -ST Multi-Channel Shared Memory FIFO Core x
2.1. Core Overview 2.2. Performance and Resource Utilization 2.3. Functional Description 2.4. Parameters 2.5. Software Programming Model 2.6. Avalon® -ST Multi-Channel Shared Memory FIFO Core Revision History
2.3. Functional Description x
2.3.1. Interfaces 2.3.2. Operation
2.5. Software Programming Model x
2.5.1. HAL System Library Support 2.5.2. Register Map
3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores x
3.1. Core Overview 3.2. Functional Description 3.3. Parameters 3.4. Register Description 3.5. Avalon® -ST Single-Clock and Dual-Clock FIFO Core Revision History
3.2. Functional Description x
3.2.1. Interfaces 3.2.2. Operating Modes 3.2.3. Fill Level 3.2.4. Thresholds
4. Avalon® -ST Serial Peripheral Interface Core x
4.1. Functional Description 4.2. Configuration 4.3. Avalon® -ST Serial Peripheral Interface Core Revision History
4.1. Functional Description x
4.1.1. Interfaces 4.1.2. Operation 4.1.3. Timing 4.1.4. Limitations
5. SPI Core x
5.1. Core Overview 5.2. Functional Description 5.3. Configuration 5.4. Software Programming Model 5.5. Example Test Code 5.6. SPI Core Revision History
5.2. Functional Description x
5.2.1. Example Configurations 5.2.2. Transmitter Logic 5.2.3. Receiver Logic 5.2.4. Host and Agent Modes
5.2.4. Host and Agent Modes x
5.2.4.1. Host Mode Operation 5.2.4.2. Agent Mode Operation 5.2.4.3. Multi-Agent Environments
5.3. Configuration x
5.3.1. Host/Agent Settings 5.3.2. Data Register Settings 5.3.3. Timing Settings 5.3.4. Synchronizer Stages
5.3.1. Host/Agent Settings x
5.3.1.1. Number of Select (SS_n) Signals 5.3.1.2. SPI Clock (sclk) Rate 5.3.1.3. Specify Delay
5.4. Software Programming Model x
5.4.1. Hardware Access Routines 5.4.2. Software Files 5.4.3. Register Map
5.4.1. Hardware Access Routines x
5.4.1.1. alt_avalon_spi_command()
5.4.3. Register Map x
5.4.3.1. rxdata Register 5.4.3.2. txdata Register 5.4.3.3. status Register 5.4.3.4. control Register 5.4.3.5. slaveselect Register 5.4.3.6. end of packet value Register
6. SPI Agent/JTAG to Avalon® Host Bridge Cores x
6.1. Core Overview 6.2. Functional Description 6.3. Parameters 6.4. SPI Agent/JTAG to Avalon® Host Bridge Cores Revision History
7. Intel eSPI Agent Core x
7.1. Functional Description 7.2. Resource Utilization 7.3. IP Parameters 7.4. Interface Signals 7.5. Registers 7.6. Peripheral Channel Avalon Interface Use Model 7.7. Intel eSPI Agent Core Revision History
7.1. Functional Description x
7.1.1. Link Layer 7.1.2. Transaction Layer 7.1.3. Channel Specific Layer 7.1.4. Port80 Implementation 7.1.5. VW message to Physical Port Implementation 7.1.6. Avalon® Memory-Mapped Interface Settings
7.1.3. Channel Specific Layer x
7.1.3.1. Peripheral Channel 7.1.3.2. Virtual Wire Channel
7.1.3.2. Virtual Wire Channel x
7.1.3.2.1. Interrupt Event
7.5. Registers x
7.5.1. Avalon® memory-mapped interface Accessible Registers 7.5.2. eSPI Interface Accessible Registers
7.5.1. Avalon® memory-mapped interface Accessible Registers x
7.5.1.1. Status Register 7.5.1.2. Control Register 7.5.1.3. Error Register
7.5.2. eSPI Interface Accessible Registers x
7.5.2.1. eSPI Status Register 7.5.2.2. Capabilities and Configuration Registers
8. eSPI to LPC Bridge Core x
8.1. Unsupported LPC Features 8.2. IP Parameters 8.3. Supported IP Clock Frequency 8.4. Functional Description 8.5. Interface Signals 8.6. Registers 8.7. eSPI to LPC Bridge Core Revision History
8.4. Functional Description x
8.4.1. FIFO Implementation 8.4.2. Transaction Ordering Rule 8.4.3. eSPI Command to LPC Cycle Type Conversion 8.4.4. SERIRQ Interrupt Event
8.6. Registers x
8.6.1. Status Register 8.6.2. Error Register
9. Ethernet MDIO Core x
9.1. Core Overview 9.2. Functional Description 9.3. Parameter 9.4. Configuration Registers 9.5. Interface Signals 9.6. Ethernet MDIO Core Revision History
9.2. Functional Description x
9.2.1. MDIO Frame Format (Clause 45) 9.2.2. MDIO Clock Generation 9.2.3. Interfaces 9.2.4. Operation
9.2.4. Operation x
9.2.4.1. Write Operation 9.2.4.2. Read Operation
10. Intel FPGA 16550 Compatible UART Core x
10.1. Core Overview 10.2. Feature Description 10.3. Software Programming Model 10.4. Address Map and Register Descriptions 10.5. Intel FPGA 16550 Compatible UART Core Revision History
10.2. Feature Description x
10.2.1. Unsupported Features 10.2.2. Interface 10.2.3. General Architecture 10.2.4. 16550 UART General Programming Flow Chart 10.2.5. Configuration Parameters 10.2.6. DMA Support 10.2.7. FPGA Resource Usage 10.2.8. Timing and Fmax 10.2.9. Avalon® -MM Agent 10.2.10. Over-run/Under-run Conditions 10.2.11. Hardware Auto Flow-Control 10.2.12. Clock and Baud Rate Selection
10.2.9. Avalon® -MM Agent x
10.2.9.1. Read behavior 10.2.9.2. Write behavior
10.2.10. Over-run/Under-run Conditions x
10.2.10.1. Overrun 10.2.10.2. Receive Overrun Behavior 10.2.10.3. Transmit Overrun Behavior 10.2.10.4. Underrun
10.3. Software Programming Model x
10.3.1. Overview 10.3.2. Supported Features 10.3.3. Unsupported Features 10.3.4. Configuration 10.3.5. 16550 UART API 10.3.6. Driver Examples
10.3.5. 16550 UART API x
10.3.5.1. Public APIs 10.3.5.2. Private APIs 10.3.5.3. UART Device Structure
10.4. Address Map and Register Descriptions x
10.4.1. rbr_thr_dll 10.4.2. ier_dlh 10.4.3. iir 10.4.4. fcr 10.4.5. lcr 10.4.6. mcr 10.4.7. lsr 10.4.8. msr 10.4.9. scr 10.4.10. afr 10.4.11. tx_low
11. UART Core x
11.1. Core Overview 11.2. Functional Description 11.3. Instantiating the Core 11.4. Software Programming Model 11.5. UART Core Revision History
11.2. Functional Description x
11.2.1. Avalon® -MM Agent Interface and Registers 11.2.2. RS-232 Interface 11.2.3. Transmitter Logic 11.2.4. Receiver Logic 11.2.5. Baud Rate Generation
11.3. Instantiating the Core x
11.3.1. Configuration Settings
11.3.1. Configuration Settings x
11.3.1.1. Baud Rate Options 11.3.1.2. Baud Rate (bps) Setting 11.3.1.3. Baud Rate Can Be Changed By Software Setting 11.3.1.4. Data Bits, Stop Bits, Parity 11.3.1.5. Synchronizer Stages 11.3.1.6. Streaming Data (DMA) Control
11.3.1.6. Streaming Data (DMA) Control x
11.3.1.6.1. Include End-of-Packet Register
11.4. Software Programming Model x
11.4.1. HAL System Library Support 11.4.2. Software Files 11.4.3. Register Map 11.4.4. Interrupt Behavior
11.4.1. HAL System Library Support x
11.4.1.1. Driver Options: Fast vs Small Implementations 11.4.1.2. ioctl() Operations 11.4.1.3. Limitations
11.4.1.1. Driver Options: Fast vs Small Implementations x
11.4.1.1.1. UART API 11.4.1.1.2. UART Device Structure
11.4.3. Register Map x
11.4.3.1. rxdata Register 11.4.3.2. txdata Register 11.4.3.3. status Register 11.4.3.4. control Register 11.4.3.5. divisor Register (Optional) 11.4.3.6. endofpacket Register (Optional)
12. JTAG UART Core x
12.1. Core Overview 12.2. Functional Description 12.3. Configuration 12.4. Software Programming Model 12.5. JTAG UART Core Revision History
12.2. Functional Description x
12.2.1. Avalon® Agent Interface and Registers 12.2.2. Read and Write FIFOs 12.2.3. JTAG Interface 12.2.4. Host-Target Connection 12.2.5. Operating System Code Page
12.3. Configuration x
12.3.1. Configuration Page
12.3.1. Configuration Page x
12.3.1.1. Write FIFO Settings 12.3.1.2. Read FIFO Settings
12.4. Software Programming Model x
12.4.1. HAL System Library Support 12.4.2. Software Files 12.4.3. Accessing the JTAG UART Core via a Host PC 12.4.4. Register Map 12.4.5. Interrupt Behavior
12.4.1. HAL System Library Support x
12.4.1.1. Driver Options: Fast vs. Small Implementations 12.4.1.2. ioctl() Operations
12.4.4. Register Map x
12.4.4.1. Data Register 12.4.4.2. Control Register
13. Intel FPGA Avalon® Mailbox Core x
13.1. Core Overview 13.2. Functional Description 13.3. Interface 13.4. HAL Driver 13.5. Intel FPGA Avalon® Mailbox Core Revision History
13.2. Functional Description x
13.2.1. Message Sending and Retrieval Process 13.2.2. Component Register Map
13.2.2. Component Register Map x
13.2.2.1. Command Register 13.2.2.2. Pointer Register 13.2.2.3. Status Register 13.2.2.4. Interrupt Masking Register
13.3. Interface x
13.3.1. Component Interface 13.3.2. Component Parameterization
13.4. HAL Driver x
13.4.1. Feature Description
13.4.1. Feature Description x
13.4.1.1. Component Configuration 13.4.1.2. Driver Implementation 13.4.1.3. Driver Examples
13.4.1.1. Component Configuration x
13.4.1.1.1. Interrupt Mode 13.4.1.1.2. Polling Mode
14. Intel FPGA Avalon® Mutex Core x
14.1. Core Overview 14.2. Functional Description 14.3. Configuration 14.4. Software Programming Model 14.5. Mutex API 14.6. Intel FPGA Avalon® Mutex Core Revision History
14.4. Software Programming Model x
14.4.1. Software Files 14.4.2. Hardware Access Routines
14.5. Mutex API x
14.5.1. altera_avalon_mutex_is_mine() 14.5.2. altera_avalon_mutex_first_lock() 14.5.3. altera_avalon_mutex_lock() 14.5.4. altera_avalon_mutex_open() 14.5.5. altera_avalon_mutex_trylock() 14.5.6. altera_avalon_mutex_unlock()
15. Intel FPGA Avalon® I2C (Host) Core x
15.1. Core Overview 15.2. Feature Description 15.3. Configuration Parameters 15.4. Interface 15.5. Registers 15.6. Reset and Clock Requirements 15.7. Functional Description 15.8. Intel FPGA Avalon® I2C (Host) Core API 15.9. Intel FPGA Avalon® I2C (Host) Core Revision History
15.2. Feature Description x
15.2.1. Supported Features 15.2.2. Unsupported Features
15.5. Registers x
15.5.1. Register Memory Map 15.5.2. Register Descriptions
15.5.2. Register Descriptions x
15.5.2.1. Transfer Command FIFO (TFR_CMD) 15.5.2.2. Receive Data FIFO (RX_DATA) 15.5.2.3. Control Register (CTRL) 15.5.2.4. Interrupt Status Enable Register (ISER) 15.5.2.5. Interrupt Status Register (ISR) 15.5.2.6. Status Register (STATUS) 15.5.2.7. TFR CMD FIFO Level (TFR CMD FIFO LVL) 15.5.2.8. RX Data FIFO Level (RX Data FIFO LVL) 15.5.2.9. SCL Low Count (SCL LOW) 15.5.2.10. SCL High Count (SCL HIGH) 15.5.2.11. SDA Hold Count (SDA HOLD)
15.7. Functional Description x
15.7.1. Overview 15.7.2. Configuring TFT_CMD Register Examples 15.7.3. I2C Serial Interface Connection 15.7.4. Avalon® -MM Agent Interface 15.7.5. Avalon® -ST Interface 15.7.6. Programming Model
15.7.2. Configuring TFT_CMD Register Examples x
15.7.2.1. 7-bit Addressing Mode 15.7.2.2. 10-bit Addressing Mode
15.7.2.1. 7-bit Addressing Mode x
15.7.2.1.1. Host Transmitter Writes 2 Bytes to Agent Receiver 15.7.2.1.2. Host Receiver Reads 2 Bytes from Agent Transmitter 15.7.2.1.3. Combine Format (Host Writes 1 Byte and Changes Direction to Read 2 Bytes)
15.7.2.2. 10-bit Addressing Mode x
15.7.2.2.1. Host Transmitter Writes 2 Bytes to Agent Receiver 15.7.2.2.2. Host Receiver Reads 2 Bytes from Agent Transmitter
15.8. Intel FPGA Avalon® I2C (Host) Core API x
15.8.1. Optional Status Retrieval API
16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core x
16.1. Core Overview 16.2. Functional Description 16.3. Platform Designer Parameters 16.4. Signals 16.5. How to Translate the Bridge's I2C Data and I2C I/O Ports to an I2C Interface 16.6. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core Revision History
16.2. Functional Description x
16.2.1. Block Diagram 16.2.2. N-byte Addressing 16.2.3. N-byte Addressing with N-bit Address Stealing 16.2.4. Read Operation 16.2.5. Write Operation 16.2.6. Interacting with Multi-Hosts
16.2.4. Read Operation x
16.2.4.1. Random Address Read 16.2.4.2. Sequential Address Read 16.2.4.3. Current Address Read
17. Intel FPGA Avalon® Compact Flash Core x
17.1. Core Overview 17.2. Functional Description 17.3. Required Connections 17.4. Software Programming Model 17.5. Intel FPGA Avalon® Compact Flash Core Revision History
17.4. Software Programming Model x
17.4.1. HAL System Library Support 17.4.2. Software Files 17.4.3. Register Maps
17.4.3. Register Maps x
17.4.3.1. Ide Registers 17.4.3.2. Ctl Registers 17.4.3.3. Cfctl Register 17.4.3.4. idectl Register
18. EPCS/EPCQA Serial Flash Controller Core x
18.1. Core Overview 18.2. Functional Description 18.3. Configuration 18.4. Interface Signals 18.5. Software Programming Model 18.6. Driver API 18.7. EPCS/EPCQA Serial Flash Controller Core Revision History
18.2. Functional Description x
18.2.1. Avalon® -MM Agent Interface and Registers
18.5. Software Programming Model x
18.5.1. HAL System Library Support 18.5.2. Software Files
19. Intel FPGA Serial Flash Controller Core x
19.1. Parameters 19.2. Registers 19.3. Nios® II and Nios® V Tools Support 19.4. Driver API 19.5. Intel FPGA Serial Flash Controller Core Revision History
19.1. Parameters x
19.1.1. Configuration Device Types 19.1.2. I/O Mode 19.1.3. Chip Selects 19.1.4. Interface Signals
19.2. Registers x
19.2.1. Register Memory Map 19.2.2. Register Descriptions
19.2.2. Register Descriptions x
19.2.2.1. FLASH_RD_STATUS 19.2.2.2. FLASH_RD_SID 19.2.2.3. FLASH_RD_RDID 19.2.2.4. FLASH_MEM_OP 19.2.2.5. FLASH_ISR 19.2.2.6. FLASH_IMR 19.2.2.7. FLASH_CHIP_SELECT
19.2.2.4. FLASH_MEM_OP x
19.2.2.4.1. Valid Sector Combination for Sector Protect and Sector Erase Command
19.2.2.4.1. Valid Sector Combination for Sector Protect and Sector Erase Command x
19.2.2.4.1.1. Sector Protect 19.2.2.4.1.2. Sector Erase
19.3. Nios® II and Nios® V Tools Support x
19.3.1. Booting Nios® II from Flash 19.3.2. Nios® II and Nios® V HAL Drivers
19.3.1. Booting Nios® II from Flash x
19.3.1.1. Flash Memory Map and Setting Nios® II Reset Vector when Using a Boot Copier 19.3.1.2. Boot Copier File 19.3.1.3. When Nios® II SBT will Append a Boot Copier 19.3.1.4. Creating HEX Programming File 19.3.1.5. Programming the Flash 19.3.1.6. Custom Boot Copiers 19.3.1.7. Executing in Place
20. Intel FPGA Serial Flash Controller II Core x
20.1. Parameters 20.2. Registers 20.3. Nios® II and Nios® V Tools Support 20.4. Driver API 20.5. Intel FPGA Serial Flash Controller II Core Revision History
20.1. Parameters x
20.1.1. Configuration Device Types 20.1.2. I/O Mode 20.1.3. Chip Selects 20.1.4. Interface Signals
20.2. Registers x
20.2.1. Register Memory Map 20.2.2. Register Descriptions
20.2.2. Register Descriptions x
20.2.2.1. FLASH_RD_STATUS 20.2.2.2. FLASH_RD_RDID 20.2.2.3. FLASH_MEM_OP 20.2.2.4. FLASH_CHIP_SELECT 20.2.2.5. EPCQ_FLAG_STATUS 20.2.2.6. DEVICE_ID_DATA_x
20.2.2.3. FLASH_MEM_OP x
20.2.2.3.1. Valid Sector Combination for Sector Protect and Sector Erase Command
20.2.2.3.1. Valid Sector Combination for Sector Protect and Sector Erase Command x
20.2.2.3.1.1. Sector Protect 20.2.2.3.1.2. Sector Erase
20.3. Nios® II and Nios® V Tools Support x
20.3.1. Booting Nios® II from Flash 20.3.2. Nios® II and Nios® V HAL Drivers
20.3.1. Booting Nios® II from Flash x
20.3.1.1. Flash Memory Map and Setting Nios® II Reset Vector when Using a Boot Copier 20.3.1.2. Boot Copier File 20.3.1.3. When Nios® II SBT will Append a Boot Copier 20.3.1.4. Creating HEX Programming File 20.3.1.5. Programming the Flash 20.3.1.6. Custom Boot Copiers 20.3.1.7. Executing in Place
21. Intel FPGA Generic QUAD SPI Controller Core x
21.1. Parameters 21.2. Registers 21.3. Nios® II and Nios® V Tools Support 21.4. Driver API 21.5. Intel FPGA Generic QUAD SPI Controller Core Revision History
21.1. Parameters x
21.1.1. Configuration Device Types 21.1.2. I/O Mode 21.1.3. Chip Selects 21.1.4. Interface Signals
21.2. Registers x
21.2.1. Register Memory Map 21.2.2. Register Descriptions
21.2.2. Register Descriptions x
21.2.2.1. FLASH_RD_STATUS 21.2.2.2. FLASH_RD_SID 21.2.2.3. FLASH_RD_RDID 21.2.2.4. FLASH_MEM_OP 21.2.2.5. FLASH_ISR 21.2.2.6. FLASH_IMR 21.2.2.7. FLASH_CHIP_SELECT
21.2.2.4. FLASH_MEM_OP x
21.2.2.4.1. Valid Sector Combination for Sector Protect and Sector Erase Command
21.2.2.4.1. Valid Sector Combination for Sector Protect and Sector Erase Command x
21.2.2.4.1.1. Sector Protect 21.2.2.4.1.2. Sector Erase
21.3. Nios® II and Nios® V Tools Support x
21.3.1. Nios® II and Nios® V HAL Drivers
22. Intel FPGA Generic QUAD SPI Controller II Core x
22.1. Parameters 22.2. Interface Signals 22.3. Registers 22.4. Nios® II and Nios® V Tools Support 22.5. Driver API 22.6. Intel FPGA Generic QUAD SPI Controller II Core Revision History
22.1. Parameters x
22.1.1. Disable Dedicated Active Serial Interface 22.1.2. Enable SPI Pins Interface 22.1.3. Enable Flash Simulation Model 22.1.4. Configuration Device Types 22.1.5. I/O Mode 22.1.6. Chip Selects
22.3. Registers x
22.3.1. Register Memory Map 22.3.2. Register Descriptions
22.3.2. Register Descriptions x
22.3.2.1. FLASH_RD_STATUS 22.3.2.2. FLASH_RD_RDID 22.3.2.3. FLASH_MEM_OP 22.3.2.4. FLASH_CHIP_SELECT 22.3.2.5. EPCQ_FLAG_STATUS 22.3.2.6. DEVICE_ID_DATA_x
22.3.2.3. FLASH_MEM_OP x
22.3.2.3.1. Valid Sector Combination for Sector Protect and Sector Erase Command
22.3.2.3.1. Valid Sector Combination for Sector Protect and Sector Erase Command x
22.3.2.3.1.1. Sector Protect 22.3.2.3.1.2. Sector Erase
22.4. Nios® II and Nios® V Tools Support x
22.4.1. Nios® II and Nios® V HAL Drivers
23. Interval Timer Core x
23.1. Core Overview 23.2. Functional Description 23.3. Configuration 23.4. Software Programming Model 23.5. Interval Timer Core API 23.6. Interval Timer Core Revision History
23.2. Functional Description x
23.2.1. Avalon® -MM Agent Interface
23.3. Configuration x
23.3.1. Timeout Period 23.3.2. Counter Size 23.3.3. Hardware Options 23.3.4. Configuring the Timer as a Watchdog Timer
23.4. Software Programming Model x
23.4.1. HAL System Library Support 23.4.2. Software Files 23.4.3. Register Map 23.4.4. Interrupt Behavior
24. Intel FPGA Avalon FIFO Memory Core x
24.1. Core Overview 24.2. Functional Description 24.3. Configuration 24.4. Software Programming Model 24.5. Programming with the Intel FPGA Avalon FIFO Memory 24.6. Intel FPGA Avalon FIFO Memory API 24.7. Intel FPGA Avalon FIFO Memory Core Revision History
24.2. Functional Description x
24.2.1. Avalon® -MM Write Agent to Avalon® -MM Read Agent 24.2.2. Avalon® -ST Sink to Avalon® -ST Source 24.2.3. Avalon® -MM Write Agent to Avalon® -ST Source 24.2.4. Avalon® -ST Sink to Avalon® -MM Read Agent 24.2.5. Status Interface 24.2.6. Clocking Modes
24.3. Configuration x
24.3.1. FIFO Settings 24.3.2. Interface Parameters 24.3.3. Interface Signals
24.4. Software Programming Model x
24.4.1. HAL System Library Support 24.4.2. Software Files
24.5. Programming with the Intel FPGA Avalon FIFO Memory x
24.5.1. Software Control 24.5.2. Software Example
24.6. Intel FPGA Avalon FIFO Memory API x
24.6.1. altera_avalon_fifo_init() 24.6.2. altera_avalon_fifo_read_status() 24.6.3. altera_avalon_fifo_read_ienable() 24.6.4. altera_avalon_fifo_read_almostfull() 24.6.5. altera_avalon_fifo_read_almostempty() 24.6.6. altera_avalon_fifo_read_event() 24.6.7. altera_avalon_fifo_read_level() 24.6.8. altera_avalon_fifo_clear_event() 24.6.9. altera_avalon_fifo_write_ienable() 24.6.10. altera_avalon_fifo_write_almostfull() 24.6.11. altera_avalon_fifo_write_almostempty() 24.6.12. altera_avalon_write_fifo() 24.6.13. altera_avalon_write_other_info() 24.6.14. altera_avalon_fifo_read_fifo() 24.6.15. altera_avalon_fifo_read_other_info()
25. On-Chip Memory (RAM and ROM) Intel FPGA IP x
25.1. Core Overview 25.2. Component-Level Design for On-Chip Memory 25.3. Platform Designer System-Level Design for On-Chip Memory 25.4. Simulation for On-Chip Memory 25.5. Quartus® Prime Project-Level Design for On-Chip Memory 25.6. Board-Level Design for On-Chip Memory 25.7. Example Design with On-Chip Memory 25.8. On-Chip Memory (RAM and ROM) Intel FPGA IP Revision History
25.2. Component-Level Design for On-Chip Memory x
25.2.1. Memory Type 25.2.2. Size 25.2.3. Read Latency 25.2.4. ROM/RAM Memory Protection 25.2.5. ECC Parameter 25.2.6. Memory Initialization
26. On-Chip Memory II (RAM or ROM) Intel FPGA IP x
26.1. Core Overview 26.2. Embedded Memory Architecture and Features 26.3. Component-Level Configurations 26.4. Interface Signals 26.5. Control and Status Registers 26.6. Software Programming Model 26.7. Platform Designer System-Level Design for On-Chip Memory II 26.8. Simulation for On-Chip Memory II 26.9. Quartus® Prime Project-Level Design for On-Chip Memory II 26.10. Board-Level Design for On-Chip Memory II 26.11. Example Design with On-Chip Memory II 26.12. On-Chip Memory II (RAM and ROM) Intel FPGA IP Revision History
26.3. Component-Level Configurations x
26.3.1. Avalon Memory-Mapped On-Chip Memory II Configuration 26.3.2. AXI-4 On-Chip Memory II Configuration
26.3.1. Avalon Memory-Mapped On-Chip Memory II Configuration x
26.3.1.1. Avalon Memory-Mapped Interface 26.3.1.2. Memory Type 26.3.1.3. Clock Enable 26.3.1.4. Size 26.3.1.5. Read During Write Mode 26.3.1.6. Read Latency 26.3.1.7. ROM/RAM Memory Protection 26.3.1.8. ECC 26.3.1.9. Memory Initialization
26.3.2. AXI-4 On-Chip Memory II Configuration x
26.3.2.1. AXI-4 Interface 26.3.2.2. Memory Type 26.3.2.3. Clock Enable 26.3.2.4. Size 26.3.2.5. Read During Write Mode 26.3.2.6. ROM/RAM Memory Protection 26.3.2.7. Memory Initialization 26.3.2.8. ECC
26.3.2.8. ECC x
26.3.2.8.1. Supported ECC Configuration 26.3.2.8.2. Supported ECC Features 26.3.2.8.3. ECC Status Reporting 26.3.2.8.4. ECC Encoder Bypass 26.3.2.8.5. Read Modify Write
26.4. Interface Signals x
26.4.1. Avalon Memory-Mapped Interface Signals 26.4.2. Avalon Memory-Mapped Interface Timing Diagram 26.4.3. AXI-4 Lite Interface Signals 26.4.4. AXI-4 Interface Signals 26.4.5. AXI Interface Timing Diagram
26.5. Control and Status Registers x
26.5.1. Register Memory Map 26.5.2. Register Descriptions
26.6. Software Programming Model x
26.6.1. Read ECC Error Status FIFO 26.6.2. Enable Encoder Bypass Feature
27. Optrex 16207 LCD Controller Core x
27.1. Core Overview 27.2. Functional Description 27.3. Software Programming Model 27.4. Optrex 16207 LCD Controller Core Revision History
27.3. Software Programming Model x
27.3.1. HAL System Library Support 27.3.2. Displaying Characters on the LCD 27.3.3. Software Files 27.3.4. Register Map 27.3.5. Interrupt Behavior
28. PIO Core x
28.1. Core Overview 28.2. Functional Description 28.3. Example Configurations 28.4. Configuration 28.5. Software Programming Model 28.6. PIO Core Revision History
28.2. Functional Description x
28.2.1. Data Input and Output 28.2.2. Edge Capture 28.2.3. IRQ Generation
28.3. Example Configurations x
28.3.1. Avalon® -MM Interface
28.4. Configuration x
28.4.1. Basic Settings 28.4.2. Input Options 28.4.3. Simulation
28.4.1. Basic Settings x
28.4.1.1. Width 28.4.1.2. Direction 28.4.1.3. Output Port Reset Value 28.4.1.4. Output Register
28.4.2. Input Options x
28.4.2.1. Edge Capture Register 28.4.2.2. Interrupt
28.5. Software Programming Model x
28.5.1. Software Files 28.5.2. Register Map 28.5.3. Interrupt Behavior 28.5.4. Software Files
28.5.2. Register Map x
28.5.2.1. data Register 28.5.2.2. direction Register 28.5.2.3. interruptmask Register 28.5.2.4. edgecapture Register 28.5.2.5. outset and outclear Register
29. PLL Cores x
29.1. Core Overview 29.2. Functional Description 29.3. Instantiating the Avalon® ALTPLL Core 29.4. Instantiating the PLL Core 29.5. Hardware Simulation Considerations 29.6. Register Definitions and Bit List 29.7. PLL Cores Revision History
29.2. Functional Description x
29.2.1. ALTPLL IP Core 29.2.2. Clock Outputs 29.2.3. PLL Status and Control Signals 29.2.4. System Reset Considerations
29.6. Register Definitions and Bit List x
29.6.1. Status Register 29.6.2. Control Register 29.6.3. Phase Reconfig Control Register
30. DMA Controller Core x
30.1. Core Overview 30.2. Functional Description 30.3. Parameters 30.4. Software Programming Model 30.5. DMA Controller Core Revision History
30.2. Functional Description x
30.2.1. Setting Up DMA Transactions 30.2.2. The Host Read and Write Ports 30.2.3. Addressing and Address Incrementing
30.3. Parameters x
30.3.1. DMA Parameters (Basic) 30.3.2. Advanced Options
30.4. Software Programming Model x
30.4.1. HAL System Library Support 30.4.2. Software Files 30.4.3. Register Map 30.4.4. Interrupt Behavior
31. Modular Scatter-Gather DMA Core x
31.1. Core Overview 31.2. Feature Description 31.3. mSGDMA Interfaces and Parameters 31.4. mSGDMA Descriptors 31.5. Register Map of mSGDMA 31.6. Programming Model 31.7. Modular Scatter-Gather DMA Prefetcher Core 31.8. Driver Implementation 31.9. Example Code Using mSGDMA Core 31.10. Modular Scatter-Gather DMA Core Revision History
31.3. mSGDMA Interfaces and Parameters x
31.3.1. Interface 31.3.2. mSGDMA Parameter Editor
31.3.1. Interface x
31.3.1.1. Descriptor Agent Port 31.3.1.2. Control and Status Register Agent Port 31.3.1.3. Response Port 31.3.1.4. Parameters
31.4. mSGDMA Descriptors x
31.4.1. Read and Write Address Fields 31.4.2. Length Field 31.4.3. Sequence Number Field 31.4.4. Read and Write Burst Count Fields 31.4.5. Read and Write Stride Fields 31.4.6. Control Field
31.5. Register Map of mSGDMA x
31.5.1. Status Register 31.5.2. Control Register 31.5.3. Write Fill Level Register 31.5.4. Read Fill Level Register 31.5.5. Response Fill Level Register 31.5.6. Write Sequence Number Register 31.5.7. Read Sequence Number Register 31.5.8. Component Configuration 1 Register 31.5.9. Component Configuration 2 Register 31.5.10. Component Type Register 31.5.11. Component Version Register
31.6. Programming Model x
31.6.1. Stop DMA Operation 31.6.2. Stop Descriptor Operation 31.6.3. Recovery from Stopped on Error and Stopped on Early Termination
31.7. Modular Scatter-Gather DMA Prefetcher Core x
31.7.1. Functional Description
31.7.1. Functional Description x
31.7.1.1. Supported Features 31.7.1.2. Architecture Overview 31.7.1.3. Descriptor Format 31.7.1.4. Registers 31.7.1.5. Interfaces 31.7.1.6. Software Programming Model 31.7.1.7. Parameters
31.7.1.3. Descriptor Format x
31.7.1.3.1. Descriptor Fields Definition 31.7.1.3.2. Descriptor Processing
31.7.1.4. Registers x
31.7.1.4.1. Register Map 31.7.1.4.2. Control Register 31.7.1.4.3. Descriptor Polling Frequency 31.7.1.4.4. Status
31.7.1.5. Interfaces x
31.7.1.5.1. Avalon® -MM Read Descriptor 31.7.1.5.2. Avalon® -MM Write Descriptor 31.7.1.5.3. Avalon® -MM CSR 31.7.1.5.4. Avalon® -ST Descriptor Source 31.7.1.5.5. Avalon® -ST Response 31.7.1.5.6. IRQ Interface
31.7.1.6. Software Programming Model x
31.7.1.6.1. Setting up Descriptor and mSGDMA Configuration Flow 31.7.1.6.2. Resetting Prefetcher Core Flow
31.8. Driver Implementation x
31.8.1. alt_msgdma_standard_descriptor_async_transfer 31.8.2. alt_msgdma_extended_descriptor_async_transfer 31.8.3. alt_msgdma_descriptor_async_transfer 31.8.4. alt_msgdma_standard_descriptor_sync_transfer 31.8.5. alt_msgdma_extended_descriptor_sync_transfer 31.8.6. alt_msgdma_descriptor_sync_transfer 31.8.7. alt_msgdma_construct_standard_st_to_mm_descriptor 31.8.8. alt_msgdma_construct_standard_mm_to_st_descriptor 31.8.9. alt_msgdma_construct_standard_mm_to_mm_descriptor 31.8.10. alt_msgdma_construct_standard_descriptor 31.8.11. alt_msgdma_construct_extended_st_to_mm_descriptor 31.8.12. alt_msgdma_construct_extended_mm_to_st_descriptor 31.8.13. alt_msgdma_construct_extended_mm_to_mm_descriptor 31.8.14. alt_msgdma_construct_extended_descriptor 31.8.15. alt_msgdma_register_callback 31.8.16. alt_msgdma_open 31.8.17. alt_msgdma_write_standard_descriptor 31.8.18. alt_msgdma_write_extended_descriptor 31.8.19. alt_msgdma_init 31.8.20. alt_msgdma_irq
32. Scatter-Gather DMA Controller Core x
32.1. Core Overview 32.2. Resource Usage and Performance 32.3. Functional Description 32.4. Parameters 32.5. Simulation Considerations 32.6. Software Programming Model 32.7. Programming with SG-DMA Controller 32.8. Scatter-Gather DMA Controller Core Revision History
32.1. Core Overview x
32.1.1. Example Systems 32.1.2. Comparison of SG-DMA Controller Core and DMA Controller Core
32.3. Functional Description x
32.3.1. Functional Blocks and Configurations 32.3.2. DMA Descriptors 32.3.3. Error Conditions
32.6. Software Programming Model x
32.6.1. HAL System Library Support 32.6.2. Software Files 32.6.3. Register Maps 32.6.4. DMA Descriptors 32.6.5. Timeouts
32.7. Programming with SG-DMA Controller x
32.7.1. Data Structure 32.7.2. SG-DMA API 32.7.3. alt_avalon_sgdma_do_async_transfer() 32.7.4. alt_avalon_sgdma_do_sync_transfer() 32.7.5. alt_avalon_sgdma_construct_mem_to_mem_desc() 32.7.6. alt_avalon_sgdma_construct_stream_to_mem_desc() 32.7.7. alt_avalon_sgdma_construct_mem_to_stream_desc() 32.7.8. alt_avalon_sgdma_enable_desc_poll() 32.7.9. alt_avalon_sgdma_disable_desc_poll() 32.7.10. alt_avalon_sgdma_check_descriptor_status() 32.7.11. alt_avalon_sgdma_register_callback() 32.7.12. alt_avalon_sgdma_start() 32.7.13. alt_avalon_sgdma_stop() 32.7.14. alt_avalon_sgdma_open()
33. SDRAM Controller Core x
33.1. Core Overview 33.2. Functional Description 33.3. Configuration 33.4. Hardware Simulation Considerations 33.5. Example Configurations 33.6. Software Programming Model 33.7. Clock, PLL and Timing Considerations 33.8. SDRAM Controller Core Revision History
33.2. Functional Description x
33.2.1. Avalon® memory-mapped interface 33.2.2. Off-Chip SDRAM Interface 33.2.3. Board Layout and Pinout Considerations 33.2.4. Performance Considerations
33.2.2. Off-Chip SDRAM Interface x
33.2.2.1. Signal Timing and Electrical Characteristics 33.2.2.2. Synchronizing Clock and Data Signals 33.2.2.3. Clock Disable Mode Support 33.2.2.4. Sharing Pins with other Avalon® memory-mapped interface Tri-State Devices
33.2.4. Performance Considerations x
33.2.4.1. Open Row Management 33.2.4.2. Sharing Data and Address Pins 33.2.4.3. Hardware Design and Target Device
33.3. Configuration x
33.3.1. Memory Profile Page 33.3.2. Timing Page
33.4. Hardware Simulation Considerations x
33.4.1. SDRAM Controller Simulation Model 33.4.2. SDRAM Memory Model
33.4.2. SDRAM Memory Model x
33.4.2.1. Using the Generic Memory Model 33.4.2.2. Using the SDRAM Manufacturer's Memory Model
33.7. Clock, PLL and Timing Considerations x
33.7.1. Factors Affecting SDRAM Timing 33.7.2. Symptoms of an Untuned PLL 33.7.3. Estimating the Valid Signal Window 33.7.4. Example Calculation
34. Tri-State SDRAM Core x
34.1. Core Overview 34.2. Feature Description 34.3. Configuration Parameter 34.4. Interface 34.5. Reset and Clock Requirements 34.6. Architecture 34.7. Intel SDRAM Tri-State Controller Core Revision History
34.2. Feature Description x
34.2.1. Block Diagram
34.3. Configuration Parameter x
34.3.1. Memory Profile Page 34.3.2. Timing Page
34.6. Architecture x
34.6.1. Avalon® -MM Agent Interface and CSR 34.6.2. Block Level Usage Model
35. Video Sync Generator and Pixel Converter Cores x
35.1. Core Overview 35.2. Video Sync Generator 35.3. Pixel Converter 35.4. Hardware Simulation Considerations 35.5. Video Sync Generator and Pixel Converter Cores Revision History
35.2. Video Sync Generator x
35.2.1. Functional Description 35.2.2. Parameters 35.2.3. Signals 35.2.4. Timing Diagrams
35.3. Pixel Converter x
35.3.1. Functional Description 35.3.2. Parameters 35.3.3. Signals
36. Intel FPGA Interrupt Latency Counter Core x
36.1. Core Overview 36.2. Feature Description 36.3. Component Interface 36.4. Component Parameterization 36.5. Software Access 36.6. Implementation Details 36.7. IP Caveats 36.8. Intel FPGA Interrupt Latency Counter Core Revision History
36.2. Feature Description x
36.2.1. Avalon® -MM Compliant CSR Registers 36.2.2. 32-bit Counter 36.2.3. Interrupt Detector
36.2.1. Avalon® -MM Compliant CSR Registers x
36.2.1.1. Control Register 36.2.1.2. Frequency Register 36.2.1.3. Counter Stop Registers 36.2.1.4. Latency Data Registers 36.2.1.5. Data Valid Registers 36.2.1.6. IRQ Active Registers
36.5. Software Access x
36.5.1. Routine for Level Sensitive Interrupts 36.5.2. Routine for Edge/Pulse Sensitive Interrupts
36.6. Implementation Details x
36.6.1. Interrupt Latency Counter Architecture
37. Performance Counter Unit Core x
37.1. Core Overview 37.2. Functional Description 37.3. Configuration 37.4. Hardware Simulation Considerations 37.5. Software Programming Model 37.6. Performance Counter API 37.7. Performance Counter Core Revision History
37.2. Functional Description x
37.2.1. Section Counters 37.2.2. Global Counter 37.2.3. Register Map 37.2.4. System Reset
37.3. Configuration x
37.3.1. Define Counters 37.3.2. Multiple Clock Domain Considerations
37.5. Software Programming Model x
37.5.1. Software Files 37.5.2. Using the Performance Counter 37.5.3. Interrupt Behavior
37.6. Performance Counter API x
37.6.1. PERF_RESET() 37.6.2. PERF_START_MEASURING() 37.6.3. PERF_STOP_MEASURING() 37.6.4. PERF_BEGIN() 37.6.5. PERF_END() 37.6.6. perf_print_formatted_report() 37.6.7. perf_get_total_time() 37.6.8. perf_get_section_time() 37.6.9. perf_get_num_starts() 37.6.10. alt_get_cpu_freq()
38. Vectored Interrupt Controller Core x
38.1. Core Overview 38.2. Functional Description 38.3. Register Maps 38.4. Parameters 38.5. Intel FPGA HAL Software Programming Model 38.6. Implementing the VIC in Platform Designer 38.7. Example Designs 38.8. Advanced Topics 38.9. Vectored Interrupt Controller Core Revision History
38.2. Functional Description x
38.2.1. External Interfaces 38.2.2. Functional Blocks 38.2.3. Daisy Chaining VIC Cores 38.2.4. Latency Information
38.2.1. External Interfaces x
38.2.1.1. clk 38.2.1.2. irq_input 38.2.1.3. interrupt_controller_out 38.2.1.4. interrupt_controller_in 38.2.1.5. csr_access
38.2.2. Functional Blocks x
38.2.2.1. Interrupt Request Block 38.2.2.2. Priority Processing Block 38.2.2.3. Vector Generation Block
38.5. Intel FPGA HAL Software Programming Model x
38.5.1. Software Files 38.5.2. Macros 38.5.3. Data Structure 38.5.4. VIC API 38.5.5. Run-time Initialization 38.5.6. Board Support Package
38.5.4. VIC API x
38.5.4.1. alt_vic_sw_interrupt_set() 38.5.4.2. alt_vic_sw_interrupt_clear() 38.5.4.3. alt_vic_sw_interrupt_status() 38.5.4.4. alt_vic_irq_set_level()
38.5.6. Board Support Package x
38.5.6.1. altera_vic_driver.enable_preemption 38.5.6.2. altera_vic_driver.enable_preemption_into_new_register_set 38.5.6.3. altera_vic_driver.enable_preemption_rs_<n> 38.5.6.4. altera_vic_driver.linker_section 38.5.6.5. altera_vic_driver.<name>.vec_size 38.5.6.6. altera_vic_driver.<name>.irq<n>_rrs 38.5.6.7. altera_vic_driver.<name>.irq<n>_ril 38.5.6.8. altera_vic_driver.<name>.irq<n>_rnmi 38.5.6.9. Default Settings for RRS and RIL 38.5.6.10. VIC BSP Design Rules for Intel FPGA HAL Implementation 38.5.6.11. RTOS Considerations
38.6. Implementing the VIC in Platform Designer x
38.6.1. Adding VIC Hardware 38.6.2. Software for VIC
38.6.1. Adding VIC Hardware x
38.6.1.1. Adding the EIC Interface Shadow Register Set 38.6.1.2. VIC Instantiation, Parameterization, and Connection
38.6.1.2. VIC Instantiation, Parameterization, and Connection x
38.6.1.2.1. Instantiation 38.6.1.2.2. Parameterization 38.6.1.2.3. VIC Connections
38.6.2. Software for VIC x
38.6.2.1. alt_ic_isr_register() versus alt_irq_register()
38.7. Example Designs x
38.7.1. Example Description 38.7.2. Example Usage 38.7.3. Software Description 38.7.4. Positioning the ISR in Vector Table 38.7.5. Latency Measurement with the Performance Counter
38.7.4. Positioning the ISR in Vector Table x
38.7.4.1. Increase the Vector Table Entry Size 38.7.4.2. Do Not Register the ISR 38.7.4.3. Insert ISR in Vector Table
38.8. Advanced Topics x
38.8.1. Real Time Latency Concerns 38.8.2. Software Interrupt
38.8.1. Real Time Latency Concerns x
38.8.1.1. Pipeline Latency 38.8.1.2. Cause Latency 38.8.1.3. Selection Latency 38.8.1.4. Funnel Latency 38.8.1.5. Compiler-Related Latency
39. Avalon® -ST Data Pattern Generator and Checker Cores x
39.1. Core Overview 39.2. Data Pattern Generator 39.3. Data Pattern Checker 39.4. Hardware Simulation Considerations 39.5. Software Programming Model 39.6. Avalon® -ST Data Pattern Generator and Checker Cores Revision History
39.2. Data Pattern Generator x
39.2.1. Functional Description 39.2.2. Configuration
39.3. Data Pattern Checker x
39.3.1. Functional Description 39.3.2. Configuration
39.5. Software Programming Model x
39.5.1. Register Maps
40. Avalon® -ST Test Pattern Generator and Checker Cores x
40.1. Core Overview 40.2. Resource Utilization and Performance 40.3. Test Pattern Generator 40.4. Test Pattern Checker 40.5. Hardware Simulation Considerations 40.6. Software Programming Model 40.7. Test Pattern Generator API 40.8. Test Pattern Checker API 40.9. Avalon® -ST Test Pattern Generator and Checker Cores Revision History
40.3. Test Pattern Generator x
40.3.1. Functional Description 40.3.2. Configuration
40.4. Test Pattern Checker x
40.4.1. Functional Description 40.4.2. Configuration
40.6. Software Programming Model x
40.6.1. HAL System Library Support 40.6.2. Software Files 40.6.3. Register Maps
40.7. Test Pattern Generator API x
40.7.1. data_source_reset() 40.7.2. data_source_init() 40.7.3. data_source_get_id() 40.7.4. data_source_get_supports_packets() 40.7.5. data_source_get_num_channels() 40.7.6. data_source_get_symbols_per_cycle() 40.7.7. data_source_set_enable() 40.7.8. data_source_get_enable() 40.7.9. data_source_set_throttle() 40.7.10. data_source_get_throttle() 40.7.11. data_source_is_busy() 40.7.12. data_source_fill_level() 40.7.13. data_source_send_data()
40.8. Test Pattern Checker API x
40.8.1. data_sink_reset() 40.8.2. data_sink_init() 40.8.3. data_sink_get_id() 40.8.4. data_sink_get_supports_packets() 40.8.5. data_sink_get_num_channels() 40.8.6. data_sink_get_symbols_per_cycle() 40.8.7. data_sink_set enable() 40.8.8. data_sink_get_enable() 40.8.9. data_sink_set_throttle() 40.8.10. data_sink_get_throttle() 40.8.11. data_sink_get_packet_count() 40.8.12. data_sink_get_symbol_count() 40.8.13. data_sink_get_error_count() 40.8.14. data_sink_get_exception() 40.8.15. data_sink_exception_is_exception() 40.8.16. data_sink_exception_has_data_error() 40.8.17. data_sink_exception_has_missing_sop() 40.8.18. data_sink_exception_has_missing_eop() 40.8.19. data_sink_exception_signalled_error() 40.8.20. data_sink_exception_channel()
41. System ID Peripheral Core x
41.1. Core Overview 41.2. Functional Description 41.3. Configuration 41.4. Software Programming Model 41.5. System ID Core Revision History
41.4. Software Programming Model x
41.4.1. alt_avalon_sysid_test()
42. Avalon® Packets to Transactions Converter Core x
42.1. Core Overview 42.2. Functional Description 42.3. Avalon® Packets to Transactions Converter Core Revision History
42.2. Functional Description x
42.2.1. Interfaces 42.2.2. Operation
43. Avalon® -ST Multiplexer and Demultiplexer Cores x
43.1. Core Overview 43.2. Multiplexer 43.3. Demultiplexer 43.4. Hardware Simulation Considerations 43.5. Software Programming Model 43.6. Avalon® -ST Multiplexer and Demultiplexer Cores Revision History
43.1. Core Overview x
43.1.1. Resource Usage and Performance
43.2. Multiplexer x
43.2.1. Functional Description 43.2.2. Parameters
43.3. Demultiplexer x
43.3.1. Functional Description 43.3.2. Parameters
44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores x
44.1. Core Overview 44.2. Functional Description 44.3. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores Revision History
44.2. Functional Description x
44.2.1. Interfaces 44.2.2. Operation— Avalon® -ST Bytes to Packets Converter Core 44.2.3. Operation— Avalon® -ST Packets to Bytes Converter Core
45. Avalon® -ST Delay Core x
45.1. Core Overview 45.2. Functional Description 45.3. Parameters 45.4. Avalon® -ST Delay Core Revision History
45.2. Functional Description x
45.2.1. Reset 45.2.2. Interfaces
46. Avalon® -ST Round Robin Scheduler Core x
46.1. Core Overview 46.2. Performance and Resource Utilization 46.3. Functional Description 46.4. Parameters 46.5. Avalon® -ST Round Robin Scheduler Core Revision History
46.3. Functional Description x
46.3.1. Interfaces 46.3.2. Operations
47. Avalon® -ST Splitter Core x
47.1. Core Overview 47.2. Functional Description 47.3. Parameters 47.4. Avalon® -ST Splitter Core Revision History
47.2. Functional Description x
47.2.1. Backpressure 47.2.2. Interfaces
48. Avalon® -MM DDR Memory Half Rate Bridge Core x
48.1. Core Overview 48.2. Resource Usage and Performance 48.3. Functional Description 48.4. Instantiating the Core in Platform Designer 48.5. Example System 48.6. Avalon® -MM DDR Memory Half Rate Bridge Core Revision History
49. Intel FPGA GMII to RGMII Converter Core x
49.1. Core Overview 49.2. Feature Description 49.3. Parameters 49.4. Intel FPGA GMII to RGMII Converter Core Interface 49.5. Functional Description 49.6. Intel FPGA HPS EMAC Interface Splitter Core 49.7. Intel FPGA GMII to RGMII Converter Core Revision History
49.2. Feature Description x
49.2.1. Supported Features 49.2.2. Unsupported Features
49.3. Parameters x
49.3.1. IP Configuration Parameter
49.5. Functional Description x
49.5.1. Architecture
49.5.1. Architecture x
49.5.1.1. Data Path 49.5.1.2. Clock Scheme
49.5.1.2. Clock Scheme x
49.5.1.2.1. Transmit 49.5.1.2.2. Receive
49.6. Intel FPGA HPS EMAC Interface Splitter Core x
49.6.1. Parameter
49.6.1. Parameter x
49.6.1.1. System Info Parameter 49.6.1.2. HDL Parameter 49.6.1.3. Interface Signals 49.6.1.4. Register 49.6.1.5. Avalon® -MM Agent Interface
49.6.1.4. Register x
49.6.1.4.1. Register Memory Map 49.6.1.4.2. Register Description
50. HPS GMII to RGMII Adapter Intel® FPGA IP x
50.1. Core Overview 50.2. Feature Description 50.3. Parameters 50.4. HPS GMII to RGMII Adapter Intel® FPGA IP Interface 50.5. Functional Description 50.6. HPS GMII to RGMII Adapter Intel® FPGA IP Revision History
50.2. Feature Description x
50.2.1. Supported Features 50.2.2. Unsupported Features
50.3. Parameters x
50.3.1. IP Configuration Parameter
50.5. Functional Description x
50.5.1. Architecture
50.5.1. Architecture x
50.5.1.1. Data Path 50.5.1.2. Clock Scheme
50.5.1.2. Clock Scheme x
50.5.1.2.1. Transmit 50.5.1.2.2. Receive
51. Intel FPGA MII to RMII Converter Core x
51.1. Supported Features 51.2. Interface Signals 51.3. Parameters 51.4. Functional Description 51.5. Intel FPGA MII to RMII Converter Core Revision History
51.4. Functional Description x
51.4.1. Clocking Scheme 51.4.2. Transmit Interface 51.4.3. Receive Interface
52. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP x
52.1. Core Overview 52.2. Feature Description 52.3. Core Architecture 52.4. Configuration Parameters 52.5. Interface 52.6. Registers 52.7. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Intel® FPGA IP Core Revision History
52.2. Feature Description x
52.2.1. Supported Features
52.3. Core Architecture x
52.3.1. Data Path 52.3.2. Clock Scheme 52.3.3. MAC Speed 52.3.4. Transmit Elastic Buffer 52.3.5. Avalon® Memory-Mapped Interface Agent Interface 52.3.6. Programming Model
52.3.4. Transmit Elastic Buffer x
52.3.4.1. GMII to MII Mode Transition
52.6. Registers x
52.6.1. Register Memory Map 52.6.2. Register Description
53. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core x
53.1. Supported Features 53.2. Functional Description 53.3. Interface Signals 53.4. Register Memory Map and Description 53.5. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core Revision History
54. Intel FPGA MSI to GIC Generator Core x
54.1. Core Overview 54.2. Background 54.3. Feature Description 54.4. Intel FPGA MSI to GIC Generator Core Revision History
54.3. Feature Description x
54.3.1. Interrupt Servicing Process 54.3.2. Registers of Component 54.3.3. Unsupported Feature
54.3.2. Registers of Component x
54.3.2.1. Status Register 54.3.2.2. Error Register 54.3.2.3. Interrupt Mask Register
55. Cache Coherency Translator Intel® FPGA IP x
55.1. Core Overview 55.2. IP Parameters 55.3. Use Case 55.4. Functional Description 55.5. Interface Signals 55.6. Clocking 55.7. Reset 55.8. Clock and Reset Signals 55.9. Register Description 55.10. Cache Coherency Translator Intel® FPGA IP Revision History
55.4. Functional Description x
55.4.1. Fixed Value 55.4.2. GPIO Mode 55.4.3. CSR Mode
56. Altera ACE5-Lite Cache Coherency Translator Intel® FPGA IP x
56.1. Core Overview 56.2. IP Parameters 56.3. Use Case 56.4. Functional Description 56.5. Interface Signals 56.6. Clocking 56.7. Reset 56.8. Clock and Reset Signals 56.9. Altera ACE5-Lite Cache Coherency Translator Intel® FPGA IP Revision History
57. Lightweight UART Core x
57.1. Core Overview 57.2. Functional Description 57.3. Configuration Parameters 57.4. Instantiating the Core 57.5. Software Programming Model 57.6. Lightweight UART Core Revision History
57.2. Functional Description x
57.2.1. Avalon® Memory-Mapped Agent Interface and Registers 57.2.2. RS-232 Interface 57.2.3. Transistor-Transistor Logic (TTL) Interface 57.2.4. Handshaking Signal (CTS/RTS Flow Control) 57.2.5. Transmitter Logic 57.2.6. Receiver Logic 57.2.7. Baud Rate Generation
57.3. Configuration Parameters x
57.3.1. Implement TXFIFO and RXFIFO in Register 57.3.2. Depth of TXFIFO and RXFIFO 57.3.3. Remaining RXFIFO Depth to Assert Almost Full 57.3.4. Include CTS/RTS
57.4. Instantiating the Core x
57.4.1. Baud Rate Options 57.4.2. Baud Rate (bps) Setting 57.4.3. Baud Rate Can Be Changed by Software Setting 57.4.4. Data Bits, Stop Bits, Parity 57.4.5. Synchronizer Stages 57.4.6. Streaming Data (DMA) Control
57.4.6. Streaming Data (DMA) Control x
57.4.6.1. Include End-of-Packet Register
57.5. Software Programming Model x
57.5.1. HAL System Library Support 57.5.2. Software Files 57.5.3. Supported Features 57.5.4. Register Map 57.5.5. Interrupt Behavior
57.5.1. HAL System Library Support x
57.5.1.1. Driver Options: Fast vs. Small Implementations 57.5.1.2. ioctl() Operations
57.5.1.1. Driver Options: Fast vs. Small Implementations x
57.5.1.1.1. UART API 57.5.1.1.2. UART Device Structure
57.5.4. Register Map x
57.5.4.1. Transmit Data FIFO (TXFIFO) 57.5.4.2. Receive data FIFO (RXFIFO) 57.5.4.3. Status Register 57.5.4.4. Control Register 57.5.4.5. Divisor Register 57.5.4.6. Endofpacket Register 57.5.4.7. RXFIFO Level Register (RXFIFO_LVL) 57.5.4.8. TXFIFO level register (TXFIFO_LVL)
1. Introduction
2. Avalon® -ST Multi-Channel Shared Memory FIFO Core
3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores
4. Avalon® -ST Serial Peripheral Interface Core
5. SPI Core
6. SPI Agent/JTAG to Avalon® Host Bridge Cores
7. Intel eSPI Agent Core
8. eSPI to LPC Bridge Core
9. Ethernet MDIO Core
10. Intel FPGA 16550 Compatible UART Core
11. UART Core
12. JTAG UART Core
13. Intel FPGA Avalon® Mailbox Core
14. Intel FPGA Avalon® Mutex Core
15. Intel FPGA Avalon® I2C (Host) Core
16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core
17. Intel FPGA Avalon® Compact Flash Core
18. EPCS/EPCQA Serial Flash Controller Core
19. Intel FPGA Serial Flash Controller Core
20. Intel FPGA Serial Flash Controller II Core
21. Intel FPGA Generic QUAD SPI Controller Core
22. Intel FPGA Generic QUAD SPI Controller II Core
23. Interval Timer Core
24. Intel FPGA Avalon FIFO Memory Core
25. On-Chip Memory (RAM and ROM) Intel FPGA IP
26. On-Chip Memory II (RAM or ROM) Intel FPGA IP
27. Optrex 16207 LCD Controller Core
28. PIO Core
29. PLL Cores
30. DMA Controller Core
31. Modular Scatter-Gather DMA Core
32. Scatter-Gather DMA Controller Core
33. SDRAM Controller Core
34. Tri-State SDRAM Core
35. Video Sync Generator and Pixel Converter Cores
36. Intel FPGA Interrupt Latency Counter Core
37. Performance Counter Unit Core
38. Vectored Interrupt Controller Core
39. Avalon® -ST Data Pattern Generator and Checker Cores
40. Avalon® -ST Test Pattern Generator and Checker Cores
41. System ID Peripheral Core
42. Avalon® Packets to Transactions Converter Core
43. Avalon® -ST Multiplexer and Demultiplexer Cores
44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores
45. Avalon® -ST Delay Core
46. Avalon® -ST Round Robin Scheduler Core
47. Avalon® -ST Splitter Core
48. Avalon® -MM DDR Memory Half Rate Bridge Core
49. Intel FPGA GMII to RGMII Converter Core
50. HPS GMII to RGMII Adapter Intel® FPGA IP
51. Intel FPGA MII to RMII Converter Core
52. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP
53. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core
54. Intel FPGA MSI to GIC Generator Core
55. Cache Coherency Translator Intel® FPGA IP
56. Altera ACE5-Lite Cache Coherency Translator Intel® FPGA IP
57. Lightweight UART Core

33.7.4. Example Calculation

This section demonstrates a calculation of the signal window for a Micron MT48LC4M32B2-7 SDRAM chip and design targeting the Stratix®  II EP2S60F672C5 device. This example uses a CAS latency (CL) of 3 cycles, and a clock frequency of 50 MHz. All SDRAM signals on the device are registered in I/O cells, enabled with the Fast Input Register and Fast Output Register logic options in the Quartus® Prime software.
Table 371.  Timing Parameters for Micron MT48LC4M32B2 SDRAM Device
Parameter Symbol Value (ns) in -7 Speed Grade
Min. Max.
Access time from CLK (pos. edge) CL = 3 tAC(3) — 5.5
CL = 2 tAC(2) — 8
CL = 1 tAC(1) — 17
Address hold time tAH 1 —
Address setup time tAS 2 —
CLK high-level width tCH 2.75 —
CLK low-level width tCL 2.75 —
Clock cycle time CL = 3 tCK(3) 7 —
CL = 2 tCK(2) 10 —
CL = 1 tCK(1) 20 —
CKE hold time tCKH 1 —
CKE setup time tCKS 2 —
CS#, RAS#, CAS#, WE#, DQM hold time tCMH 1 —
CS#, RAS#, CAS#, WE#, DQM setup time tCMS 2 —
Data-in hold time tDH 1  
Data-in setup time tDS 2  
Data-out high-impedance time CL = 3 tHZ(3)   5.5
CL = 2 tHZ(2) — 8
CL = 1 tHZ(1) — 17
Data-out low-impedance time tLZ 1 —
Data-out hold time tOH 2.5  

The FPGA I/O Timing Parameters table below shows the relevant timing information, obtained from the Timing Analyzer section of the Quartus® Prime Compilation Report. The values in the table are the maximum or minimum values among all device pins related to the SDRAM. The variance in timing between the SDRAM pins on the device is small (less than 100 ps) because the registers for these signals are placed in the I/O cell.

Table 372.  FPGA I/O Timing Parameters
Parameter Symbol Value (ns)
Clock period tCLK 20
Minimum clock-to-output time tCO_MIN 2.399
Maximum clock-to-output time tCO_MAX 2.477
Maximum hold time after clock tH_MAX –5.607
Maximum setup time before clock tSU_MAX 5.936

You must compile the design in the Quartus® Prime software to obtain the I/O timing information for the design. Although Intel FPGA device family datasheets contain generic I/O timing information for each device, the Quartus® Prime Compilation Report provides the most precise timing information for your specific design.

The timing values found in the compilation report can change, depending on fitting, pin location, and other Quartus® Prime logic settings. When you recompile the design in the Quartus® Prime software, verify that the I/O timing has not changed significantly.

The following examples illustrate the calculations from figures Maximum SDRAM Clock Lag and Maximum Lead also using the values from the Timing Parameters and FPGA I/O Timing Parameters table.

The SDRAM clock can lag the controller clock by the lesser of Read Lag or Write Lag:

Read Lag = tOH(SDRAM) – tH_MAX(FPGA)

= 2.5 ns – (–5.607 ns) = 8.107 ns

or

Write Lag = tCLK – tCO_MAX(FPGA) – tDS(SDRAM)

= 20 ns – 2.477 ns – 2 ns = 15.523 ns

The SDRAM clock can lead the controller clock by the lesser of Read Lead or Write Lead:

Read Lead = tCO_MIN(FPGA) – tDH(SDRAM)

= 2.399 ns – 1.0 ns = 1.399 ns

or

Write Lead = tCLK – tHZ(3)(SDRAM) – tSU_MAX(FPGA)

= 20 ns – 5.5 ns – 5.936 ns = 8.564 ns

Therefore, for this example you can shift the phase of the SDRAM clock from –8.107 ns to 1.399 ns relative to the controller clock. Choosing a phase shift in the middle of this window results in the value (–8.107 + 1.399)/2 = –3.35 ns.

Level Two Title