Added new Enable Native XCVR PHY ADME parameter for Arria 10 variations.. |
Upgrading the IP core to incorporate this feature is optional. This change does not affect the top-level signals of the IP core. |
This parameter exposes control of transceiver configuration features. |
Changed behavior of irx_err signal. Previously, if the IP core could not determine the burst in which the error occurred, it asserted the irx_err signal anyway, and the client could also not determine the associated burst. Now, if the IP core cannot determine the burst in which an error occurred, it does not assert the irx_err signal. If it can determine the burst in which an error occurred, it asserts the irx_err signal during the end of burst cycle (when it also asserts irx_eob). |
This change ensures that apparent errors that occur during Idle cycles do not cause the irx_err signal to assert. Upgrading the IP core to incorporate this feature is optional. If you upgrade your IP core you should be aware of the change in signal behavior. |
Refer to 100G Interlaken IP Core Signal Changes v15.1 table. |
Added hardware design example for Arria 10 variations. |
A hardware design example is now available with tArria 10 variations of the 100G Interlaken IP core. |
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Modified instructions to generate legacy testbench. |
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