Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP Cores Release Notes

ID 683110
Date 7/19/2024
Public
Document Table of Contents

1.7.4. ROM: 1-PORT Intel® FPGA IP v20.1.0

Table 22.  v20.1.0 2020.10.12
Quartus® Prime Version Description Impact
20.3

Removed support for Use Stratix M512 emulation logic cell style for the LCs memory block type in the Stratix® 10 and Agilex™ 7 devices.

You are required to either change to default logic cell style or switch to non-LCs memory block type in the Stratix® 10 and Agilex™ 7 devices.
Added "X" propagation support in simulation model for the Stratix® 10 devices.
Table 23.  v20.1.0 2020.08.03
Quartus® Prime Version Description Impact
20.1 Enabled the In-System Memory Content Editor (ISMCE) support in the Agilex™ 7 devices. This change is optional. If you do not upgrade your IP, it does not have this new feature.