5G LDPC Intel® FPGA IP User Guide

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ID 683107
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 5G LDPC Intel® FPGA IP 2. Getting Started with the Intel® FPGA IP 3. Designing with the 5G LDPC Intel® FPGA IP 4. 5G LDPC Intel® FPGA IP Functional Description 5. Parameter Optimization for the 5G LDPC IP 6. 5G LDPC IP User Guide Archive 7. Document Revision History for the 5G LDPC Intel® FPGA IP User Guide
1. About the 5G LDPC Intel® FPGA IP x
1.1. 5G LDPC Intel® FPGA IP Features 1.2. 5G LDPC Intel® FPGA IP Device Family Support 1.3. 5G LDPC IP Release Information 1.4. 5G LDPC IP Performance and Resource Utilization
2. Getting Started with the Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G LDPC IP IP Timeout Behavior
3. Designing with the 5G LDPC Intel® FPGA IP x
3.1. Generating a 5G LDPC Intel® FPGA IP 3.2. Simulating the 5G LDPC IP RTL 3.3. 5G LDPC Simulation Results
4. 5G LDPC Intel® FPGA IP Functional Description x
4.1. 5G LDPC Decoder 4.2. 5G LDPC Encoder 4.3. Avalon Streaming Interfaces in DSP Intel FPGA IP
4.1. 5G LDPC Decoder x
4.1.1. 5G LDPC Decoder Signals 4.1.2. 5G LDPC Decoder Data Formats 4.1.3. 5G LDPC IP Decoder Parameters
4.2. 5G LDPC Encoder x
4.2.1. 5G LDPC Encoder Signals 4.2.2. 5G LDPC Encoder Data Formats
5. Parameter Optimization for the 5G LDPC IP x
5.1. C++ and MATLAB Software Models
5.1. C++ and MATLAB Software Models x
5.1.1. Running the 5G LDPC IP C++ Models 5.1.2. Running the 5G LDPC Decoder and Encoder MATLAB Model in the Design Example
1. About the 5G LDPC Intel® FPGA IP
2. Getting Started with the Intel® FPGA IP
3. Designing with the 5G LDPC Intel® FPGA IP
4. 5G LDPC Intel® FPGA IP Functional Description
5. Parameter Optimization for the 5G LDPC IP
6. 5G LDPC IP User Guide Archive
7. Document Revision History for the 5G LDPC Intel® FPGA IP User Guide

3.1. Generating a 5G LDPC Intel® FPGA IP

To include the IP in a design, generate the IP in the Quartus® Prime software. Or optionally, you can generate a design example that includes the generated 5G LDPC IP, a C++ model, a MATLAB model, simulation scripts, and test data.
  1. Create a New Quartus® Prime project
  2. Open IP Catalog.
  3. Select DSP > Error Detection and Correction > 5G LDPC Intel® FPGA IP and click Add
  4. Enter a name for your IP variant and click Create.
    Figure 3. IP Variant File Name
    The name is for both the top-level RTL module and the corresponding .ip file.
    The parameter editor for this IP appears.
  5. Choose your parameters.
    You can choose Encoder or Decoder and select decoder parameters.
    Figure 4. 5G LDPC Parameter Editor
  6. For an optional design example, click Generate Example Design.
    The software creates files for MATLAB, C, or RTL simulations in the target directory. The software does not generate a hardware example.
    Figure 5. Design Example Directory Structure
  7. Click Generate HDL.
Quartus® Prime generates the RTL and the files necessary to instantiate the IP in your design and synthesize it.
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