5G LDPC Intel® FPGA IP User Guide

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ID 683107
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 5G LDPC Intel® FPGA IP 2. Getting Started with the Intel® FPGA IP 3. Designing with the 5G LDPC Intel® FPGA IP 4. 5G LDPC Intel® FPGA IP Functional Description 5. Parameter Optimization for the 5G LDPC IP 6. 5G LDPC IP User Guide Archive 7. Document Revision History for the 5G LDPC Intel® FPGA IP User Guide
1. About the 5G LDPC Intel® FPGA IP x
1.1. 5G LDPC Intel® FPGA IP Features 1.2. 5G LDPC Intel® FPGA IP Device Family Support 1.3. 5G LDPC IP Release Information 1.4. 5G LDPC IP Performance and Resource Utilization
2. Getting Started with the Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G LDPC IP IP Timeout Behavior
3. Designing with the 5G LDPC Intel® FPGA IP x
3.1. Generating a 5G LDPC Intel® FPGA IP 3.2. Simulating the 5G LDPC IP RTL 3.3. 5G LDPC Simulation Results
4. 5G LDPC Intel® FPGA IP Functional Description x
4.1. 5G LDPC Decoder 4.2. 5G LDPC Encoder 4.3. Avalon Streaming Interfaces in DSP Intel FPGA IP
4.1. 5G LDPC Decoder x
4.1.1. 5G LDPC Decoder Signals 4.1.2. 5G LDPC Decoder Data Formats 4.1.3. 5G LDPC IP Decoder Parameters
4.2. 5G LDPC Encoder x
4.2.1. 5G LDPC Encoder Signals 4.2.2. 5G LDPC Encoder Data Formats Encoder Input Data Format Encoder Input Control Formats (msg_mode[11:0]) Encoder Output Data Format
5. Parameter Optimization for the 5G LDPC IP x
5.1. C++ and MATLAB Software Models
5.1. C++ and MATLAB Software Models x
5.1.1. Running the 5G LDPC IP C++ Models 5.1.2. Running the 5G LDPC Decoder and Encoder MATLAB Model in the Design Example
1. About the 5G LDPC Intel® FPGA IP
2. Getting Started with the Intel® FPGA IP
3. Designing with the 5G LDPC Intel® FPGA IP
4. 5G LDPC Intel® FPGA IP Functional Description
5. Parameter Optimization for the 5G LDPC IP
6. 5G LDPC IP User Guide Archive
7. Document Revision History for the 5G LDPC Intel® FPGA IP User Guide

4.2.2. 5G LDPC Encoder Data Formats

Encoder Input Data Format

The 5G LDPC Encoder IP incoming data on a 384-bit bus (msg). The IP clocks in data with K b clocks, where K b = 22 for BG1 and K b = 6, 8, 9, or 10 for BG2. The IP accepts mode information on the clock with msg_sop and msg_vld both asserted.

The width of the input message bus, msg[383:0], is 384 bits. In each clock cycle, only Z LSBs. are valid, you must set the rest of the MSBs to zeros.

Table 22.  Encoder Input Data Format for Base Graph 1, Z=64, K b = 22; message = [M0, M1, …, M1407]
msg[383:0] clock cycle
0 1 ... 20 21
msg[0] M0 M64 ... M1280 M1344
msg[1] M1 M65 ... M1281 M1345
... ... ... ... ... ...
msg[63] M63 M127 ... M1343 M1407
msg[64] 0 0 ... 0 0
... ... ... ... ... ...
msg[383] 0 0 0 0 0

Encoder Input Control Formats (msg_mode[11:0])

Table 23.  Z Selection (msg_mode[5:0])
msg_mode[5:0] Z msg_mode[5:0] Z
0 2 26 48
1 3 27 52
2 4 28 56
3 5 29 60
4 6 30 64
5 7 31 72
6 8 32 80
7 9 33 88
8 10 34 96
9 11 35 104
10 12 36 112
11 13 37 120
12 14 38 128
13 15 39 144
14 16 40 160
15 18 41 176
16 20 42 192
17 22 43 208
18 24 44 224
19 26 45 240
20 28 46 256
21 30 47 288
22 32 48 320
23 36 49 352
24 40 50 384
25 44 X X
Table 24.  Code Rate, Base Graph, Kb Selection (msg_mode[11:6])For base graph 2, Kb can be 6, 8, 9, or 10. The encoder automatically inserts the (10 - Kb) * Z filler bits for the encoder input data (the message) before encoding happens. Then the IP removes the filler bits from the encoder output data (the codeword).
Code Rate

Base Graph 1

Kb = 22

msg_mode [11:9]=000

Base Graph 2

Kb = 6

msg_mode [11:9]=001

Base Graph 2

Kb = 8

msg_mode [11:9]=011

Base Graph 2

Kb = 9

msg_mode [11:9]=101

Base Graph 2

Kb = 10

msg_mode [11:9]=111

1/5

msg_mode[8:6]=000

 X 001000 011000 101000 111000

1/3

msg_mode[8:6]=001

 000001 001001 011001 101001 111001

2/5

msg_mode[8:6]=010

 000010 001010 011010 101010 111010

1/2

msg_mode[8:6]=011

 000011 001011 011011 101011 111011

2/3

msg_mode[8:6]=100

 000100 001100 011100 101100 111100

22/30 (~3/4)

msg_mode[8:6]=101

 000101 X X X X

22/27 (~5/6)

msg_mode[8:6]=110

 000110 X X X X

22/25 (~8/9)

msg_mode[8:6]=111

 000111 X X X X

Encoder Output Data Format

The width of the output codeword bus, cw[383:0], is 384 bits. It takes (nb - 2) clock cycles to output the codeword. Each clock cycle, only Z LSBs are valid, the rest of the MSBs are 0s.

Table 25.  Encoder Output Data Format for Base Graph 1, Z=64, Kb = 22, CR=1/3, codeword = [CW0, CW1, …, CW4223]
cw[383:0] clock cycle
0 1 ... 64 65
cw[0] CW0 CW64 ... CW4096 CW4160
cw[1] CW1 CW65 ... CW4097 CW4161
... ... ... ... ... ...
cw[63] CW63 CW127 ... CW4159 CW4223
cw[64] 0 0 ... 0 0
... ... ... ... ... ...
cw[383] 0 0 0 0 0
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