5G LDPC Intel® FPGA IP User Guide

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ID 683107
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 5G LDPC Intel® FPGA IP 2. Getting Started with the Intel® FPGA IP 3. Designing with the 5G LDPC Intel® FPGA IP 4. 5G LDPC Intel® FPGA IP Functional Description 5. Parameter Optimization for the 5G LDPC IP 6. 5G LDPC IP User Guide Archive 7. Document Revision History for the 5G LDPC Intel® FPGA IP User Guide
1. About the 5G LDPC Intel® FPGA IP x
1.1. 5G LDPC Intel® FPGA IP Features 1.2. 5G LDPC Intel® FPGA IP Device Family Support 1.3. 5G LDPC IP Release Information 1.4. 5G LDPC IP Performance and Resource Utilization
2. Getting Started with the Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G LDPC IP IP Timeout Behavior
3. Designing with the 5G LDPC Intel® FPGA IP x
3.1. Generating a 5G LDPC Intel® FPGA IP 3.2. Simulating the 5G LDPC IP RTL 3.3. 5G LDPC Simulation Results
4. 5G LDPC Intel® FPGA IP Functional Description x
4.1. 5G LDPC Decoder 4.2. 5G LDPC Encoder 4.3. Avalon Streaming Interfaces in DSP Intel FPGA IP
4.1. 5G LDPC Decoder x
4.1.1. 5G LDPC Decoder Signals 4.1.2. 5G LDPC Decoder Data Formats 4.1.3. 5G LDPC IP Decoder Parameters
4.2. 5G LDPC Encoder x
4.2.1. 5G LDPC Encoder Signals 4.2.2. 5G LDPC Encoder Data Formats
5. Parameter Optimization for the 5G LDPC IP x
5.1. C++ and MATLAB Software Models
5.1. C++ and MATLAB Software Models x
5.1.1. Running the 5G LDPC IP C++ Models 5.1.2. Running the 5G LDPC Decoder and Encoder MATLAB Model in the Design Example
1. About the 5G LDPC Intel® FPGA IP
2. Getting Started with the Intel® FPGA IP
3. Designing with the 5G LDPC Intel® FPGA IP
4. 5G LDPC Intel® FPGA IP Functional Description
5. Parameter Optimization for the 5G LDPC IP
6. 5G LDPC IP User Guide Archive
7. Document Revision History for the 5G LDPC Intel® FPGA IP User Guide

2.1.2. 5G LDPC IP IP Timeout Behavior

All IP in a device time out simultaneously when the most restrictive evaluation time is reached. If a design has more than one IP, the time-out behavior of the other IP may mask the time-out behavior of a specific IP .

For IP, the untethered time-out is 1 hour; the tethered time-out value is indefinite. Your design stops working after the hardware evaluation time expires. The Quartus Prime software uses Intel® FPGA IP Evaluation Mode Files (.ocp) in your project directory to identify your use of the Intel® FPGA IP Evaluation Mode evaluation program. After you activate the feature, do not delete these files.

When the evaluation time expires, for the encoders cw goes low and rst_n goes low; for decoders source_data goes low, reset_n goes low.

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