Quartus® Prime Pro Edition User Guide: Design Recommendations

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ID 683082
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. Recommended HDL Coding Styles 2. Recommended Design Practices 3. Managing Metastability with the Quartus® Prime Software 4. Quartus® Prime Pro Edition User Guide: Design Recommendations Archive A. Quartus® Prime Pro Edition User Guides
1. Recommended HDL Coding Styles x
1.1. Using Provided HDL Templates 1.2. Instantiating IP Cores in HDL 1.3. Inferring Multipliers and DSP Functions 1.4. Inferring Memory Functions from HDL Code 1.5. Register and Latch Coding Guidelines 1.6. General Coding Guidelines 1.7. Designing with Low-Level Primitives 1.8. Cross-Module Referencing (XMR) in HDL Code 1.9. Using force Statements in HDL Code 1.10. Recommended HDL Coding Styles Revision History
1.1. Using Provided HDL Templates x
1.1.1. Inserting HDL Code from a Provided Template
1.3. Inferring Multipliers and DSP Functions x
1.3.1. Inferring Multipliers 1.3.2. Inferring Multiply-Accumulator and Multiply-Adder Functions
1.4. Inferring Memory Functions from HDL Code x
1.4.1. Inferring RAM functions from HDL Code 1.4.2. Inferring ROM Functions from HDL Code 1.4.3. Inferring Shift Registers in HDL Code 1.4.4. Inferring FIFOs in HDL Code
1.4.1. Inferring RAM functions from HDL Code x
1.4.1.1. Use Synchronous Memory Blocks 1.4.1.2. Avoid Unsupported Reset and Control Conditions 1.4.1.3. Check Read-During-Write Behavior 1.4.1.4. Controlling RAM Inference and Implementation 1.4.1.5. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior 1.4.1.6. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior 1.4.1.7. Simple Dual-Port, Dual-Clock Synchronous RAM 1.4.1.8. True Dual-Port Synchronous RAM 1.4.1.9. Mixed-Width Dual-Port RAM 1.4.1.10. RAM with Byte-Enable Signals SystemVerilog Simple Dual-Port Synchronous RAM with Byte Enable VHDL Simple Dual-Port Synchronous RAM with Byte Enable 1.4.1.11. Specifying Initial Memory Contents at Power-Up
1.4.3. Inferring Shift Registers in HDL Code x
1.4.3.1. Simple Shift Register 1.4.3.2. Shift Register with Evenly Spaced Taps
1.4.4. Inferring FIFOs in HDL Code x
1.4.4.1. Dual Clock FIFO Example in Verilog HDL 1.4.4.2. Dual Clock FIFO Timing Constraints
1.5. Register and Latch Coding Guidelines x
1.5.1. Register Power-Up Values 1.5.2. Secondary Register Control Signals Such as Clear and Clock Enable 1.5.3. Latches
1.5.1. Register Power-Up Values x
1.5.1.1. Specifying a Power-Up Value
1.5.3. Latches x
1.5.3.1. Avoid Unintentional Latch Generation 1.5.3.2. Inferring Latches Correctly
1.6. General Coding Guidelines x
1.6.1. Tri-State Signals 1.6.2. Clock Multiplexing 1.6.3. Adder Trees 1.6.4. State Machine HDL Guidelines 1.6.5. Multiplexer HDL Guidelines 1.6.6. Cyclic Redundancy Check Functions 1.6.7. Comparator HDL Guidelines 1.6.8. Counter HDL Guidelines
1.6.3. Adder Trees x
1.6.3.1. Architectures with 6-Input LUTs in Adaptive Logic Modules 1.6.3.2. Change Adder Tree Styles
1.6.4. State Machine HDL Guidelines x
1.6.4.1. State Machine Processing 1.6.4.2. State Machine Power-Up 1.6.4.3. Verilog HDL State Machines 1.6.4.4. VHDL State Machines
1.6.4.3. Verilog HDL State Machines x
1.6.4.3.1. Verilog-2001 State Machine Coding Example 1.6.4.3.2. SystemVerilog State Machine Coding Example
1.6.4.4. VHDL State Machines x
1.6.4.4.1. VHDL State Machine Coding Example
1.6.5. Multiplexer HDL Guidelines x
1.6.5.1. Quartus® Prime Software Option for Multiplexer Restructuring 1.6.5.2. Multiplexer Types 1.6.5.3. Implicit Defaults in IF Statements 1.6.5.4. default or OTHERS CASE Assignment
1.6.5.2. Multiplexer Types x
1.6.5.2.1. Binary Multiplexers 1.6.5.2.2. Selector Multiplexers 1.6.5.2.3. Priority Multiplexers
1.6.6. Cyclic Redundancy Check Functions x
1.6.6.1. If Performance is Important, Optimize for Speed 1.6.6.2. Use Separate CRC Blocks Instead of Cascaded Stages 1.6.6.3. Use Separate CRC Blocks Instead of Allowing Blocks to Merge 1.6.6.4. Take Advantage of Latency if Available 1.6.6.5. Save Power by Disabling CRC Blocks When Not in Use 1.6.6.6. Initialize the Device with the Synchronous Load (sload) Signal
2. Recommended Design Practices x
2.1. Following Synchronous FPGA Design Practices 2.2. HDL Design Guidelines 2.3. Use Clock and Register-Control Architectural Features 2.4. Implementing Embedded RAM 2.5. Design Assistant Design Rule Checking 2.6. Recommended Design Practices Revision History
2.1. Following Synchronous FPGA Design Practices x
2.1.1. Implementing Synchronous Designs 2.1.2. Asynchronous Design Hazards
2.2. HDL Design Guidelines x
2.2.1. Considerations for the Hyperflex® FPGA Architecture 2.2.2. Optimizing Combinational Logic 2.2.3. Optimizing Clocking Schemes 2.2.4. Optimizing Physical Implementation and Timing Closure 2.2.5. Optimizing Power Consumption 2.2.6. Managing Design Metastability
2.2.2. Optimizing Combinational Logic x
2.2.2.1. Avoid Combinational Loops 2.2.2.2. Avoid Unintended Latch Inference 2.2.2.3. Avoid Delay Chains in Clock Paths 2.2.2.4. Use Synchronous Pulse Generators
2.2.3. Optimizing Clocking Schemes x
2.2.3.1. Register Combinational Logic Outputs 2.2.3.2. Avoid Asynchronous Clock Division 2.2.3.3. Avoid Ripple Counters 2.2.3.4. Use Multiplexed Clocks 2.2.3.5. Use Gated Clocks 2.2.3.6. Use Synchronous Clock Enables
2.2.3.5. Use Gated Clocks x
2.2.3.5.1. Recommended Clock-Gating Methods
2.2.4. Optimizing Physical Implementation and Timing Closure x
2.2.4.1. Planning Physical Implementation 2.2.4.2. Planning FPGA Resources 2.2.4.3. Optimizing for Timing Closure 2.2.4.4. Optimizing Critical Timing Paths
2.3. Use Clock and Register-Control Architectural Features x
2.3.1. Use Global Reset Resources 2.3.2. Use Global Clock Network Resources 2.3.3. Use Clock Region Assignments to Optimize Clock Constraints 2.3.4. Avoid Asynchronous Register Control Signals
2.3.1. Use Global Reset Resources x
2.3.1.1. Use Synchronous Resets 2.3.1.2. Using Asynchronous Resets 2.3.1.3. Use Synchronized Asynchronous Reset
2.3.3. Use Clock Region Assignments to Optimize Clock Constraints x
2.3.3.1. Clock Region Assignments in Stratix® 10 Devices 2.3.3.2. Clock Region Assignments in Arria® 10 and Older Device Families
2.5. Design Assistant Design Rule Checking x
2.5.1. Setting Up Design Assistant 2.5.2. Running Design Assistant During Compilation 2.5.3. Running Design Assistant in Analysis Mode 2.5.4. Cross-Probing from Design Assistant 2.5.5. Managing Design Assistant Rules 2.5.6. Design Assistant Rule Categories
2.5.1. Setting Up Design Assistant x
2.5.1.1. Design Assistant Rule Severity Levels
2.5.2. Running Design Assistant During Compilation x
2.5.2.1. Opening Design Assistant Rule Help
2.5.3. Running Design Assistant in Analysis Mode x
2.5.3.1. Launching Design Assistant from Chip Planner 2.5.3.2. Launching Design Assistant from Timing Analyzer
2.5.4. Cross-Probing from Design Assistant x
2.5.4.1. Cross-Probing from Design Assistant to Timing Analyzer 2.5.4.2. Cross-Probing from Design Assistant to Visualization Tools
2.5.5. Managing Design Assistant Rules x
2.5.5.1. Changing the Default Number of Violations per Rule 2.5.5.2. Enabling Rules for Specific Compiler Stages 2.5.5.3. Specifying Rule Parameters for a Specific Compiler Stage 2.5.5.4. Modifying Rule Severity Levels 2.5.5.5. Waiving Design Assistant Rules 2.5.5.6. Design Assistant Tags
2.5.5.5. Waiving Design Assistant Rules x
2.5.5.5.1. Creating Design Assistant Waivers 2.5.5.5.2. Design Assistant Waiver Dialog Box 2.5.5.5.3. Deleting Design Assistant Waivers 2.5.5.5.4. Design Assistant Waiver Tcl Commands 2.5.5.5.5. drc::add_waiver Command 2.5.5.5.6. drc::get_waivers Command 2.5.5.5.7. drc::report_waivers Command
3. Managing Metastability with the Quartus® Prime Software x
3.1. Metastability Analysis in the Quartus® Prime Software 3.2. Metastability and MTBF Reporting 3.3. MTBF Optimization 3.4. Reducing Metastability Effects 3.5. Scripting Support 3.6. Managing Metastability 3.7. Managing Metastability with the Quartus® Prime Software Revision History
3.1. Metastability Analysis in the Quartus® Prime Software x
3.1.1. Data Synchronization Register Chains 3.1.2. Identify Synchronizers for Metastability Analysis 3.1.3. How Timing Constraints Affect Synchronizer Identification and Metastability Analysis
3.2. Metastability and MTBF Reporting x
3.2.1. Metastability Reports 3.2.2. Synchronizer Data Toggle Rate in MTBF Calculation
3.2.1. Metastability Reports x
3.2.1.1. MTBF Summary Report 3.2.1.2. Synchronizer Summary Report 3.2.1.3. Synchronizer Chain Statistics Report in the Timing Analyzer
3.2.1.1. MTBF Summary Report x
3.2.1.1.1. Typical and Worst-Case MTBF of Design 3.2.1.1.2. Synchronizer Chains 3.2.1.1.3. Increasing Available Settling Time
3.3. MTBF Optimization x
3.3.1. Synchronization Register Chain Length
3.4. Reducing Metastability Effects x
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer 3.4.2. Force the Identification of Synchronization Registers 3.4.3. Set the Synchronizer Data Toggle Rate 3.4.4. Optimize Metastability During Fitting 3.4.5. Increase the Length of Synchronizers to Protect and Optimize 3.4.6. Increase the Number of Stages Used in Synchronizers 3.4.7. Select a Faster Speed Grade Device
3.5. Scripting Support x
3.5.1. Identifying Synchronizers for Metastability Analysis 3.5.2. Synchronizer Data Toggle Rate in MTBF Calculation 3.5.3. report_metastability and Tcl Command 3.5.4. MTBF Optimization 3.5.5. Synchronization Register Chain Length
1. Recommended HDL Coding Styles
2. Recommended Design Practices
3. Managing Metastability with the Quartus® Prime Software
4. Quartus® Prime Pro Edition User Guide: Design Recommendations Archive
A. Quartus® Prime Pro Edition User Guides

1.4.1.10. RAM with Byte-Enable Signals

The RAM code examples in this section show SystemVerilog and VHDL code that infers RAM with controls for writing single bytes into the memory word, or byte-enable signals.

Synthesis models byte-enable signals by creating write expressions with two indexes, and writing part of a RAM "word." With these implementations, you can also write more than one byte at once by enabling the appropriate byte enables.

Verilog-1995 doesn't support mixed-width RAMs because the standard lacks a multi-dimensional array to model the different read width, write width, or both. Verilog-2001 doesn't support mixed-width RAMs because this type of logic requires multiple packed dimensions. Different synthesis tools may differ in their support for these memories. This section describes the inference rules for Quartus® Prime Pro Edition synthesis.

Refer to the Quartus® Prime HDL templates for parameterized examples that you can use for different address widths, and true dual port RAM examples with two read ports and two write ports.

SystemVerilog Simple Dual-Port Synchronous RAM with Byte Enable 

module byte_enabled_simple_dual_port_ram  
( 
    input we, clk,
    input [ADDRESS_WIDTH-1:0] waddr, raddr,// address width = 6 
    input [NUM_BYTES-1:0] be, // 4 bytes per word
    input [(BYTE_WIDTH * NUM_BYTES -1):0] wdata, // byte width = 8, 4 bytes per word
    output reg [(BYTE_WIDTH * NUM_BYTES -1):0] q // byte width = 8, 4 bytes per word
);

   parameter ADDRESS_WIDTH = 6;
   parameter DEPTH = 2**ADDRESS_WIDTH;
   parameter BYTE_WIDTH = 8;
   parameter NUM_BYTES = 4;

   // use a multi-dimensional packed array
   //to model individual bytes within the word
   logic [NUM_BYTES-1:0][BYTE_WIDTH-1:0] ram[0:DEPTH-1]; 
     // # words = 1 << address width

	// port A
   always@(posedge clk)
   begin
	   if(we) begin
          for (int i = 0; i < NUM_BYTES; i = i + 1) begin
            if(be[i]) ram[waddr][i] <= wdata[i*BYTE_WIDTH +: BYTE_WIDTH];
          end
      end
      q <= ram[raddr];
   end
endmodule

VHDL Simple Dual-Port Synchronous RAM with Byte Enable

library ieee;
use ieee.std_logic_1164.all;
library work;

entity byte_enabled_simple_dual_port_ram is
generic (DEPTH      : integer := 64;
         NUM_BYTES  : integer :=  4;
         BYTE_WIDTH : integer :=  8
);
port (
    we, clk : in  std_logic;
    waddr, raddr : in  integer range 0 to DEPTH -1 ;     -- address width = 6
    be   : in  std_logic_vector (NUM_BYTES-1 downto 0);   -- 4 bytes per word
    wdata: in  std_logic_vector((NUM_BYTES * BYTE_WIDTH -1) downto 0);   -- width = 32
    q    : out std_logic_vector((NUM_BYTES * BYTE_WIDTH -1) downto 0) ); -- width = 32
end byte_enabled_simple_dual_port_ram;

architecture rtl of byte_enabled_simple_dual_port_ram is

    --  build up 2D array to hold the memory
    type word_t is array (0 to NUM_BYTES-1) of std_logic_vector(BYTE_WIDTH-1 downto 0);
    type ram_t is array (0 to DEPTH-1) of word_t;

    signal ram : ram_t;
    signal q_local : word_t;

    begin  -- Re-organize the read data from the RAM to match the output
        unpack: for i in 0 to NUM_BYTES-1 generate    
            q(BYTE_WIDTH*(i+1) - 1 downto BYTE_WIDTH*i) <= q_local(i);
    end generate unpack;
        
    -- port A
    process(clk)
    begin
        if(rising_edge(clk)) then 
            if(we = '1') then
                for I in (NUM_BYTES-1) downto 0 loop
                    if(be(I) = '1') then
                        ram(waddr)(I) <= wdata(((I+1)*BYTE_WIDTH-1) downto I*BYTE_WIDTH);
                    end if;
                 end loop;
            end if;
            q_local <= ram(raddr);
        end if;
    end process;  
end rtl;
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