Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation

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ID 683080
Date 2/05/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Intel FPGA Simulation Basics 2. Siemens EDA QuestaSim* Simulator Support 3. Synopsys VCS* and VCS MX Support 4. Cadence Xcelium* Parallel Simulator Support 5. Aldec Active-HDL and Riviera-PRO Support A. Intel® Quartus® Prime Standard Edition User Guides
1. Intel FPGA Simulation Basics x
1.1. Intel FPGA Simulation Essential Elements 1.2. Overview of Simulation Tool Flow 1.3. Simulation Tool Flow 1.4. Supported Simulation Types 1.5. Supported Simulation Flows 1.6. Supported Hardware Description Languages 1.7. Supported Simulators 1.8. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) 1.9. Intel FPGA Simulation Basics Revision History
1.2. Overview of Simulation Tool Flow x
1.2.1. Compilation Stage 1.2.2. Elaboration Stage 1.2.3. Simulation Stage
1.3. Simulation Tool Flow x
1.3.1. Specifying Logical Libraries 1.3.2. Compiling Files Into Library Directories 1.3.3. The Intel® Quartus® Prime Simulation Library 1.3.4. Understanding Elaboration 1.3.5. Commands To Configure and Run Simulation 1.3.6. Intel FPGA Simulation Generic Workflow
1.3.1. Specifying Logical Libraries x
1.3.1.1. Why Do We Need Logical Library Names?
1.3.2. Compiling Files Into Library Directories x
1.3.2.1. Inputs to Compilation Commands 1.3.2.2. Order of Files for Compilation Commands 1.3.2.3. Compilation Command Line Options 1.3.2.4. Module Definitions in Library Directories
1.3.3. The Intel® Quartus® Prime Simulation Library x
1.3.3.1. The Intel® Quartus® Prime Simulation Library Compiler 1.3.3.2. Running the Simulation Library Compiler in a Terminal 1.3.3.3. Running the Simulation Library Compiler in the GUI 1.3.3.4. Finding Logical Library Names in Simulation Library Compiler Output
1.3.4. Understanding Elaboration x
1.3.4.1. Elaboration Binding Phase 1.3.4.2. Elaboration Checks 1.3.4.3. Elaboration Options
1.8. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) x
1.8.1. Setting Up NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) 1.8.2. Running RTL Simulation (NativeLink Flow) 1.8.3. Running Gate-Level Simulation (NativeLink Flow)
2. Siemens EDA QuestaSim* Simulator Support x
2.1. Quick Start Example (QuestaSim* with Verilog) 2.2. QuestaSim* Simulator Guidelines 2.3. QuestaSim* Simulation Setup Script Example 2.4. Sourcing QuestaSim* Simulator Setup Scripts 2.5. Unsupported Features 2.6. Siemens EDA QuestaSim* Simulator Support Revision History
2.2. QuestaSim* Simulator Guidelines x
2.2.1. Passing Parameter Information from Verilog HDL to VHDL 2.2.2. Viewing Simulation Messages 2.2.3. Generating Signal Activity Data for Power Analysis 2.2.4. Viewing Simulation Waveforms
2.2.3. Generating Signal Activity Data for Power Analysis x
2.2.3.1. Generating Standard Delay Output for Power Analysis
3. Synopsys VCS* and VCS MX Support x
3.1. Quick Start Example (VCS with Verilog) 3.2. VCS and VCS MX Guidelines 3.3. VCS Simulation Setup Script Example 3.4. Sourcing Synopsys VCS* MX Simulator Setup Scripts 3.5. Sourcing Synopsys VCS* Simulator Setup Scripts 3.6. Synopsys VCS* and VCS MX Support Revision History
3.2. VCS and VCS MX Guidelines x
3.2.1. Simulating Transport Delays 3.2.2. Disabling Timing Violation on Registers 3.2.3. Generating Power Analysis Files
4. Cadence Xcelium* Parallel Simulator Support x
4.1. Generating Simulator Setup Script Templates 4.2. Sourcing Cadence Xcelium* Simulator Setup Scripts 4.3. Cadence Xcelium* Parallel Simulator Support Revision History
5. Aldec Active-HDL and Riviera-PRO Support x
5.1. Quick Start Example (Active-HDL VHDL) 5.2. Aldec Active-HDL and Riviera-PRO Guidelines 5.3. Using Simulation Setup Scripts 5.4. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 5.5. Aldec Active-HDL* and Riviera-PRO * Support Revision History
5.2. Aldec Active-HDL and Riviera-PRO Guidelines x
5.2.1. Compiling SystemVerilog Files 5.2.2. Disabling Timing Violation on Registers
Answers to Top FAQs
1. Intel FPGA Simulation Basics
2. Siemens EDA QuestaSim* Simulator Support
3. Synopsys VCS* and VCS MX Support
4. Cadence Xcelium* Parallel Simulator Support
5. Aldec Active-HDL and Riviera-PRO Support
A. Intel® Quartus® Prime Standard Edition User Guides

1.5. Supported Simulation Flows

The Intel® Quartus® Prime software supports scripted and specialized simulation flows.
Table 3.  Simulation Flows
Simulation Flow Description
Scripted Simulation Flows Scripted simulation supports custom control of all aspects of simulation, such as custom compilation commands, or multipass simulation flows. Use a version-independent top-level simulation script that sources Intel® Quartus® Prime-generated IP simulation setup scripts. The Intel® Quartus® Prime software can generate a combined simulator setup script for all IP cores, for each supported simulator.
NativeLink Simulation Flow NativeLink automates Intel® Quartus® Prime integration with your EDA simulator. Setup NativeLink to generate simulation scripts, compile simulation libraries, and automatically launch your simulator following design compilation. Specify your own compilation, elaboration, and simulation scripts for testbench and simulation model files. Do not use NativeLink if you require direct control over every aspect of simulation.
Specialized Simulation Flows Specialized simulation flows support various design scenarios:
  • For simulation of example designs, refer to the example design pr IP documentation.
  • For simulation of Platform Designer designs, refer to Simulating Platform Designer (Standard) Systems in Intel® Quartus® Prime Standard Edition User Guide: Platform Designer .
  • For simulation of the Nios® V processor, refer to the Nios V Embedded Processor Design Handbook.
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