F-Tile Interlaken Intel® FPGA IP Design Example User Guide

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ID 683069
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling and Configuring the Hardware Design Example 1.6. Testing the Hardware Design Example
2. Design Example Description x
2.1. Design Example Components 2.2. Analog Parameters Settings 2.3. Design Example Flow 2.4. Interface Signals 2.5. Register Map 2.6. Reset
1. Quick Start Guide
2. Design Example Description
3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide

2.2. Analog Parameters Settings

For Intel Quartus Prime Pro Edition Software version 23.2 and earlier versions, F-tile transceiver analog parameters are set through Intel Quartus Prime software settings file (.qsf).

From Quartus Prime Pro Edition Software version 23.3 onwards, a GUI allows you to set the analog parameters of F-tile transceivers. The figures show the FGT and FHT Analog Parameters Tab.
Figure 7. Analog Parameters Tab for FGT
Figure 8. Analog Parameters Tab for FHT

When you are using the development kit, the default analog value may not match your hardware setup. Altera recommends that you use the following settings when generating example design for Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit.

Table 6.   Recommended Analog Settings for FGT Designs
Parameter Value
FGT TXEQ Post Tap 1, 1.0 step size 0
FGT TXEQ Main Tap, 1.0 step size 35
FGT TXEQ Pre Tap 1, 1.0 step size 5
FGT TXEQ Pre Tap 2, 1.0 step size 0
Select FGT RX Onchip Termination RX_ONCHIP_TERMINATION_R_2 (100ohms)
Enable FGT RX AC Couple ENABLE
Enable FGT VSR mode

VSR is set when insertion loss < 10dB, RX auto adaptation is ON for >= 23 Gbps NRZ or any PAM4 rate:

  • For insertion loss < 5 dB, set to VSR_MODE_LOW_LOSS
  • For insertion loss > 5 dB but < 10 dB, set to VSR_MODE_HIGH_LOSS
  • Otherwise Quartus Prime sets VSR_MODE_DISABLE by default for rates below < 23 Gbps where VSR is not required.
Table 7.   Recommended Analog Settings for FHT Designs
Simulator Instructions
Enable FHT TX P&N Invert Enabled
Enable FHT TXOUT Tristate Disabled
Select FHT TX Termination TXTERM_OFFSET_P0 (90ohms)
Enable FHT RX P&N Invert Enabled
Select FHT RX Termination RXTERM_OFFSET_P0 (90ohms)
Select FHT external AC Cap EXTERNAL_AC_CAP_ENABLE
Post-Cursor 4, 0.25 step size 0.0
Post-Cursor 3, 0.25 step size 0.0
Post-Cursor 2, 0.25 step size 0.0
Post-Cursor 1, 0.5 step size -2
Main-Cursor, 0.5 step size 18
Pre-Cursor 1, 0.5 step size -4
Post-Cursor 2, 0.25 step size -2
Post-Cursor 3, 0.25 step size 0.0
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