F-Tile Interlaken Intel® FPGA IP Design Example User Guide

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ID 683069
Date 1/14/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling and Configuring the Hardware Design Example 1.6. Testing the Hardware Design Example
2. Design Example Description x
2.1. Design Example Components 2.2. Design Example Flow 2.3. Interface Signals 2.4. Register Map 2.5. Reset
1. Quick Start Guide
2. Design Example Description
3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide

2.3. Interface Signals

Table 6.  Design Example Interface Signals
Port Name Direction Width (Bits) Description
mgmt_clk Input 1 System clock input. Clock frequency must be 100 MHz.
pll_ref_clk Input 1 Transceiver reference clock. Drives the RX CDR PLL.
rx_pin Input Number of lanes Receiver SERDES data pin.
tx_pin Output Number of lanes Transmit SERDES data pin.
rx_pin_n 4 Input Number of lanes Receiver SERDES data pin.
tx_pin_n 4 Output Number of lanes Transmit SERDES data pin.
mac_clk_pll_ref Input 1 This signal must be driven by a PLL and must use the same clock source that drives the pll_ref_clk.

This signal is only available in PAM4 mode device variations.

usr_pb_reset_n Input 1 System reset.

4 Only available in PAM4 variants.
Level Two Title