AN 705: Scalable 10G Ethernet MAC using 1G/10G PHY

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ID 683066
Date 5/13/2016
Public
Document Table of Contents
Document Table of Contents x
1. Scalable 10G Ethernet MAC using 1G/10G PHY
1. Scalable 10G Ethernet MAC using 1G/10G PHY x
1.1. Features 1.2. Parameters 1.3. Block Diagrams 1.4. Components 1.5. Requirements 1.6. Design Example Walkthrough 1.7. Design Example Testbench 1.8. Clocking Scheme 1.9. Reset Scheme 1.10. Interface Signals 1.11. Register Map 1.12. Known Issues 1.13. Document Revision History
1.6. Design Example Walkthrough x
1.6.1. Setting Up the Design Examples 1.6.2. Changing Number of Channels 1.6.3. Configuring PHY Speed 1.6.4. IP Regeneration
1.6.3. Configuring PHY Speed x
1.6.3.1. Changing Speed between 10G and 1G in 1000BaseX mode 1.6.3.2. Changing Speed between 1G, 100M, and 10M SGMII
1.7. Design Example Testbench x
1.7.1. Testbench Components 1.7.2. Testbench Files 1.7.3. Simulating Testbench 1.7.4. Test Case
1.7.3. Simulating Testbench x
1.7.3.1. Using ModelSim Simulator 1.7.3.2. Using VCS Simulator
1.7.4. Test Case x
1.7.4.1. Test Scenario for Design Example without IEEE 1588v2 1.7.4.2. Test Scenario for Design Example with IEEE 1588v2
1.7.4.2. Test Scenario for Design Example with IEEE 1588v2 x
1.7.4.2.1. Testcase 1 1.7.4.2.2. Testcase 2 1.7.4.2.3. Testcase 3
1.8. Clocking Scheme x
1.8.1. Clocking Diagram 1.8.2. Sync-E Support
1.8.2. Sync-E Support x
1.8.2.1. Enable Ref Clock Sharing 1.8.2.2. Disable Ref Clock Sharing
1.9. Reset Scheme x
1.9.1. Design Example without IEEE 1588v2 1.9.2. Design Example with IEEE 1588v2 1.9.3. Internal PHY PLL Powerdown Connection Scheme
1.9.1. Design Example without IEEE 1588v2 x
1.9.1.1. Channel Level Reset Scheme 1.9.1.2. Multi-Channel Level Reset Scheme
1.9.2. Design Example with IEEE 1588v2 x
1.9.2.1. Channel Level Reset Scheme 1.9.2.2. Multi-Channel Level Reset Scheme
1.10. Interface Signals x
1.10.1. Clock and Reset Interface Signals 1.10.2. Avalon-MM Interface Signals 1.10.3. Avalon-ST Interface Signals 1.10.4. PHY Interface Signals 1.10.5. MDIO Interface Signals 1.10.6. IEEE 1588v2 Timestamp Interface Signals 1.10.7. Packet Classifier Interface Signals 1.10.8. ToD Interface Signals
1.11. Register Map x
1.11.1. Master TOD 1.11.2. 1G TOD 1.11.3. 10G TOD 1.11.4. PHY 1.11.5. 1G/10G MAC
1. Scalable 10G Ethernet MAC using 1G/10G PHY

1.7.4.2.1. Testcase 1

This testcase simulates manual speed change between 10G/1G/100M/10M in SGMII/1000Base-X mode with auto negotiation disabled using circular loopback configuration.

  • Parameter in default_test_parameter.sv file: SGMII_1000BASEX (1-SGMII, 0-1000BaseX) to select between SGMII and 1000BaseX mode.
  • To change number of channels, modify the parameter NUM_CHANNELS in default_test_params_pkg.sv file
Figure 7. Channel Waveform for Speed_sel, Avalon_st, XGMII ,GMII and MII Interface
  1. Force all of the channel to 10G mode by setting speed_sel =0. You can observe the data through the XGMII interface .
  2. After all 7 data packets sent and received by avalon_st RX of the channel, the design issues write operation to the csr interface to change to another speed mode.
  3. Continue with 1G mode by setting the speed_sel=1 and the data will be observed in GMII interface.
  4. For 100M, set speed_sel=2 and 10M, speed_sel=3. These mode transmissions of data happens in MII interfaces.
  5. For each speed mode, the test case runs in circular loopback sequence. The data flows starting with channel0 followed by channel1, channel 2, channel 3, then loopback to channel 2, channel 1 and channel 0.
  6. After the simulation stop, user can refer to the transcript window for channel0 MAC TX and RX Statistic counter result.
    Figure 8. MAC TX and RX Statistic Counter Results 
    # ------------------------
# Channel         0: TX Statistics
# ------------------------
# 	framesOK                          = 28
# 	framesErr                         = 0
# 	framesCRCErr                      = 0
# 	octetsOK                          = 2088
# 	pauseMACCtrlFrames                = 0
# 	ifErrors                          = 0
# 	unicastFramesOK                   = 28
# 	unicastFramesErr                  = 0
# 	multicastFramesOK                 = 0
# 	multicastFramesErr                = 0
# 	broadcastFramesOK                 = 0
# 	broadcastFramesErr                = 0
# 	etherStatsOctets                  = 2688
# 	etherStatsPkts                    = 28
# 	etherStatsUndersizePkts           = 0
# 	etherStatsOversizePkts            = 0
# 	etherStatsPkts64Octets            = 4
# 	etherStatsPkts65to127Octets       = 16
# 	etherStatsPkts128to255Octets      = 8
# 	etherStatsPkts256to511Octet       = 0
# 	etherStatsPkts512to1023Octets     = 0
# 	etherStatsPkts1024to1518Octets    = 0
# 	etherStatsPkts1519OtoXOctets      = 0
# 	etherStatsFragments               = 0
# 	etherStatsJabbers                 = 0
# 	etherStatsCRCErr                  = 0
# 	unicastMACCtrlFrames              = 0
# 	multicastMACCtrlFrames            = 0
# 	broadcastMACCtrlFrames            = 0
# 
# ------------------------
# Channel         0: RX Statistics
# ------------------------
# 	framesOK                          = 28
# 	framesErr                         = 0
# 	framesCRCErr                      = 0
# 	octetsOK                          = 2088
# 	pauseMACCtrlFrames                = 0
# 	ifErrors                          = 0
# 	unicastFramesOK                   = 28
# 	unicastFramesErr                  = 0
# 	multicastFramesOK                 = 0
# 	multicastFramesErr                = 0
# 	broadcastFramesOK                 = 0
# 	broadcastFramesErr                = 0
# 	etherStatsOctets                  = 2688
# 	etherStatsPkts                    = 28
# 	etherStatsUndersizePkts           = 0
# 	etherStatsOversizePkts            = 0
# 	etherStatsPkts64Octets            = 4
# 	etherStatsPkts65to127Octets       = 16
# 	etherStatsPkts128to255Octets      = 8
# 	etherStatsPkts256to511Octet       = 0
# 	etherStatsPkts512to1023Octets     = 0
# 	etherStatsPkts1024to1518Octets    = 0
# 	etherStatsPkts1519OtoXOctets      = 0
# 	etherStatsFragments               = 0
# 	etherStatsJabbers                 = 0
# 	etherStatsCRCErr                  = 0
# 	unicastMACCtrlFrames              = 0
# 	multicastMACCtrlFrames            = 0
# 	broadcastMACCtrlFrames            = 0
# 
#
# Simulation PASSED
If all the total 28 packets have been received successfully to channel 0 Avalon_st RX interface, the transcript will display Simulation PASSED.
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