Developer Reference

Migrating OpenCL™ FPGA Designs to SYCL*

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ID 767849
Date 3/31/2023
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Document Table of Contents
Document Table of Contents x
Migrating OpenCL™ FPGA Designs to SYCL* FPGA Design Flow Modify Your Design Flags, Attributes, Directives, and Extensions Histogram Design Example Walkthrough Additional Information Document Revision History for Migrating OpenCL FPGA Designs to SYCL*
Migrating OpenCL™ FPGA Designs to SYCL* x
Overview Prerequisites
Modify Your Design x
Basic Modifications Advanced Modifications
Basic Modifications x
Host Code Modification Device Code Modification
Advanced Modifications x
Host Code Modification Device Code Modification
Device Code Modification x
C++ Features in Device Code
Flags, Attributes, Directives, and Extensions x
General Information Flags FPGA Board-Specific Flags Compiler Flags Optimization Flags Memory Attributes Loop Directives Floating Point Optimizations Kernel Attributes Intra-kernel Registered Assignment Function Channels/Pipes APIs LSU Attributes
Histogram Design Example Walkthrough x
OpenCL Sample Code SYCL Sample Code SYCL Sample Code With Explicit Data Movement
Document Revision History for Migrating OpenCL FPGA Designs to SYCL* x
Notices and Disclaimers
Migrating OpenCL™ FPGA Designs to SYCL*
FPGA Design Flow
Modify Your Design
Flags, Attributes, Directives, and Extensions
Histogram Design Example Walkthrough
Additional Information
Document Revision History for Migrating OpenCL FPGA Designs to SYCL*

Channels/Pipes APIs

Channels/pipes allow passing data between kernels and synchronizing kernels with high efficiency and low latency. They allow kernels to communicate directly with each other using on-chip FIFO buffers implemented using FPGA memory resources. The compiler supports concurrent kernel execution with out-of-order queues that allows launching kernels concurrently with a single command queue. Using channels/pipes for data movement between concurrently executing kernels allows for data transfer without waiting for kernel completion, which can significantly increase the throughput of your design. Refer to Pipes and Pipes Extension topics in the FPGA Optimization Guide for Intel oneAPI Toolkits for additional information.

The following table depicts how to implement channels/pipes in OpenCL and SYCL:

Channels/Pipes
OpenCL SYCL 
channel int my_pipe __attribute__((depth(8))); 
write_channel_intel(my_pipe, &write_data); // blocking 
read_data = read_channel_intel(my_pipe, &success_code); // non-blocking
 
using my_pipe = ext::intel::pipe<class some_pipe, int, 8>; 
my_pipe::write(write_data); // blocking 
read_data = my_pipe::read(&success_code); // non-blocking

I/O Pipes

I/O Pipe Construction
OpenCL SYCL 
pipe int read_io_pipe __attribute__((depth(8), io(“io_pipe_in”)));

pipe int write_io_pipe __attribute__((depth(8), io(“io_pipe_out”)));
 
struct read_io_pipe_id {
  // id=index to “io_pipe_in” in board_spec.xml
  static constexpr unsigned id = 0;
};

struct write_io_pipe_id {
  // id=index to “io_pipe_out” in board_spec.xml
  static constexpr unsigned id = 1;
};

using read_io_pipe = intel::kernel_readable_io_pipe<read_io_pipe_id, int, 8>;

using write_io_pipe = intel::kernel_writeable_io_pipe<write_io_pipe, int, 8>;
Parent topic: Flags, Attributes, Directives, and Extensions
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