From Slow to Go: Optimize FPGA Development & Performance

FPGA development can be slow for two primary reasons:

1. Compile time.
2. Lack of intuitive tools that streamline bottleneck removal and optimize a design for the FPGA fabric without requiring you to have years of Register-Transfer Level (RTL) design experience.

Attend this session to see how the Intel® FPGA Add-on for oneAPI Base Toolkit can solve these issues. FPGA software engineers Tanner Young-Schultz and Adonay Berhe cover these topics:

• Introduce an iterative, software-friendly way of performance tuning without the need for full hardware bitstream compilation.
• Discuss how to identify performance bottlenecks and read static report files in oneAPI FPGA designs.
• Perform quick compilations and program the applications iteratively for the FPGA.
• Showcase several optimization techniques defined in DPC++ to get better performance out of the design.

• Sign up for an Intel® Tiber™ AI Cloud account—a free development sandbox with access to the latest Intel hardware and oneAPI software.
• Explore oneAPI including developer opportunities and benefits.

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