Intel® oneAPI DPC++/C++ Compiler Documentation

  

Documentation & Code Samples

Documentation

View Current Intel oneAPI DPC++/C++ Compiler Documentation

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Code Samples

C++ with SYCL* for GPU Offload

Simple-Add Programming Methods
A Hello-World-type sample adds two large vectors of integers and verifies the results. Learn how the most basic code in C++ offloads computations to a GPU using Unified Shared Memory (USM) and buffers.

Sepia Filter
Convert a color image to a monochromatic sepia tone image by offloading each compute-intensive pixel conversion using C++ with code that's compliant with SYCL for CPUs and GPUs.

Mandelbrot
Learn how to use C++ with code that's compliant with SYCL for offloading computations to a GPU. Optimize and improve processing time using parallelism.

C++ and OpenMP*

Accelerate Mandelbrot with OpenMP
Learn how to accelerate program performance with Single Instruction Multiple Data (SIMD) and parallelization using OpenMP to calculate the Mandelbrot set.

Use ISO3DFD for OpenMP Offload
ISO3DFD is a 3D stencil that simulates wave propagating in a 3D isotropic medium. Use it to understand common challenges and techniques when targeting OpenMP Offload devices, like GPUs.

 

FPGA Samples

Get Started
This tutorial shows how to compile code for FPGAs that is compliant with SYCL by using a simple vector addition.

Database Acceleration
This reference design demonstrates how to use an FPGA to accelerate database queries for a data-warehouse schema derived from the TPC-H* benchmark.

Stream I/O Channels with Minimum Variance Distortionless Response (MVDR) Beamforming
This reference design demonstrates how to use I/O streaming using SYCL on an FPGA for a large system.

Gzip Compression
Use this reference design to implement a compression algorithm optimized for FPGAs.

QR Decomposition of Matrices
This reference design demonstrates high-performance QR decomposition of real and complex matrices on an FPGA.

 

DPC++ FPGA Code Samples Navigation Guide

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{"limitDisplayedContent":"showAll","collectionRelationTags":{"relations":{"EXCLUDE":["etm-08dd1c4874304c9b9987050a09dd8567","etm-906567252bdc432bbaeb908fabef076f","etm-05429363730b40109b394df6a76dd677","etm-3baf460d15b141cfba51bdf58d2f2496","etm-96a2a467cd514dff85b6c153b364b0fa","etm-2f5e76b4e5e64d90a794e6a9d8dc26fd","etm-fc274692325e497dba29db02e84821c2","etm-80b662df26a3410eb1ecf99114bc569b","etm-ead3671d63584869ab0df9a593366522","etm-72cbbe7d977c407e9bd60dc9a5a2d0c2","etm-86fd3d3462554a56b8e3c223be8417e1","etm-c216d58933fc4051a502694b29828faa","etm-6f8479a5b1ce453c957fa689bfed124f","etm-454697a6b0ca41e8a0f6606316e92b7c"],"AND":["etm-086ec8c4b4074875b84ba0e35d214cf5","etm-6b088d69d83243a0aa3b986645a7e74b","etm-de1eecabf3594abd81ce16a352e18faf"]},"featuredIds":[]},"collectionId":"729079","resultPerPage":80.0,"filters":[{"facetId":"ContentType","type":"ContentType","deprecated":true,"name":"ContentType","position":0},{"facetId":"@stm_10306_en","field":"stm_10306_en","type":"hierarchical","basePath":"Operating System","displayName":"Operating System","deprecated":false,"rootFilter":"","position":1},{"facetId":"@stm_10357_en","field":"stm_10357_en","type":"specific","basePath":"Programming Language","displayName":"Programming Language","deprecated":false,"rootFilter":"","position":2}],"coveoRequestHardLimit":"1000","accessDetailsPagePath":"/content/www/us/en/secure/design/internal/access-details.html","collectionGuids":["etm-086ec8c4b4074875b84ba0e35d214cf5","etm-6b088d69d83243a0aa3b986645a7e74b","etm-de1eecabf3594abd81ce16a352e18faf"],"cardView":false,"sorting":"Newest","defaultImagesPath":"/content/dam/www/public/us/en/images/uatable/default-icons","coveoMaxResults":5000,"coveoSplitSize":500,"fpgaFacetRootPaths":"{\"fpgadevicefamily\":[\"Primary Content Tagging\",\"Intel® FPGAs\",\"Intel® Programmable Devices\"],\"quartusedition\":[\"Primary Content Tagging\",\"Intel® FPGAs\",\"Intel® Quartus Software\"],\"quartusaddon\":[\"Primary Content Tagging\",\"Intel® FPGAs\",\"Intel® Quartus Software - Add-ons\"],\"fpgaplatform\":[\"Primary Content Tagging\",\"Intel® FPGAs\",\"Intel® FPGA Platforms\"]}","newWrapperPageEnabled":true,"descendingSortingForNumericalFacetsName":"[\"Intel® Quartus® Prime Pro Edition\",\"Intel® Quartus® Prime Lite Edition\",\"Intel® Quartus® Prime Standard Edition\",\"Quartus® II Subscription Edition\",\"Quartus® II Web Edition\"]","columnsConfiguration":{"idColumn":false,"dateColumn":false,"versionColumn":false,"contentTypeColumn":false,"columnsMaxSize":0},"dynamicColumnsConfiguration":[{"name":"DynamicColumn_id","type":"id","gtv":"ID","width":60,"selected":true},{"name":"DynamicColumn_date","type":"date","gtv":"Date","width":60,"selected":true},{"name":"DynamicColumn_version","type":"version","gtv":"Version","width":135,"selected":true}],"updateCollateralMetadataEnabled":true,"relatedAssetsEnable":true,"disableExpandCollapseAll":false,"enableRelatedAssetsOnExpandAll":false,"disableBlueBanner":false,"isICS":false,"isUPE":false}