Intel® FPGA Device Plugin

Documentation

The FPGA device plugin is part of a collection of Intel® device plugins for Kubernetes. It enables users to deploy workload to use FPGA in a Kubernetes environment easily.

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Overview

In the past, using FPGAs has required specialist programming skilss, including a good understanding of how the hardware works, to configure each accelerator. Thanks to the latest developments in software and the FPGA ecosystems, it's much easier to use FPGAs today. The Intel FPGA plugin supports the Intel® Programmable Acceleration cards with Intel® Arria® 10 FPGA and Intel® Stratix® 10 FPGAs in Kubernetes environment.

The FPGA device plugin supports the Open Programmable Acceleration Engine (OPAE) framework and OpenCL™ code. It is designed for pre-programmed accelerators, orchestration programming, and access control.

Design and Architecture

The FPGA plugin is comprised of the following modules:

FPGA device plugin is responsible for discovering and reporting FPGA devices to the Kubelet. During the allocation phase, it instructs Kubelet about device nodes to be accessed by the container and sets the annotation that is later on passed to CRI to trigger programming by the CRI-O hook.
FPGA prestart CRI-O hook is triggered by pod annotation set by the FPGA device plugin. It performs discovery of the requested FPGA function bitstream and then programs FPGA devices based on the environment variables in the workload description.
FPGA admission controller webhook is responsible for performing mapping from user-friendly function IDs to the Interface ID and Bitstream ID that are required for FPGA programming CRI-O hook. Mappings are stored in namespaced custom resource definition (CRD) objects, therefore the admission controller also performs access control, determining which bitstream can be used for which namespace. The admission controller also keeps the user from bypassing namespaced mapping restrictions, by denying admission of any pods that are trying to use internal knowledge of Interface ID or Bitstream ID environment variables used by the prestart hook.

FPGA Plugin Modes

The FPGA plugin set can run in one of two modes:

region mode, where the plugins locate and advertise regions of the FPGA, and facilitate programing of those regions with the requested bistreams.

af mode, where the FPGA bitstreams are already loaded onto the FPGA, and the plugins discover and advertises the existing Accelerator Functions (AF).

af mode, where the FPGA bitstreams are already loaded onto the FPGA, and the plugins discover and advertises the existing Accelerator Functions (AF).