Intel® oneAPI DPC++/C++ Compiler 2022 Release Notes

This document summarizes new and changed product features and includes notes about features and problems not described in the product documentation.

Where to Find the Release

Please follow the steps to download the toolkit from the Base Toolkit Download page and follow the installation instructions to install.

oneAPI 2022.3.1, Compiler Release 2022.2.1

Intel® oneAPI DPC++/C++ Compiler 2022.2.1 has been updated to include functional and security updates. Users should update to the latest version as it becomes available.

oneAPI 2022.3, Compiler Release 2022.2.0

New Features and Improvements

• OpenCL CPU RT will load TBB library with full path in Windows registry as precedence option, or read TBB path from the configuration file as a secondary option. Users who use the oneAPI installer will not be impacted since the oneTBB installer package in oneAPI will install the TBB registry key. Users who use the Compiler CONDA package will not be impacted either since the TBB path will be configured automatically in the configuration file. However, in other scenarios, OpenCL CPU RT will fail to load TBB since there is no TBB registry key installed and the TBB file in the configuration file is not set by default. The solution is: 
  • Configuration files are located in the same folder as the OCL RT file (intelocl64.dll). Please select the corresponding device configuration file and edit it, and make sure you have already configured the targeted device, otherwise, OCL RT will load two devices but use the first one by default.
    • cl.cfg for CPU device
    • cl.fpga_emu.cfg for FPGA emulator.
  • At the bottom of the file, there is a field named “CL_CONFIG_TBB_DLL_PATH,” to which you can add your TBB DLL path. For example: CL_CONFIG_TBB_DLL_PATH = c:\your_TBB_install_path
  • Users need to be aware when configuring cl.cfg and cl.fpga_emu.cfg
    • If users configure both cl.cfg and cl.fpga_emu.cfg, the TBB location in them should be the same value.
    • Quotation marks should not be added to the location value of CL_CONFIG_TBB_DLL_PATH.
• When using 'dpcpp' as the compiler driver on Windows, the expectation is for Linux command line compatibility and behaviors. An update has been performed for 'dpcpp' which improves the Linux compatibility and may impact expected behaviors if using 'dpcpp' for MSVC compatible command lines. When MSVC-compatible command line behaviors are desired, please use 'dpcpp-cl' as the compiler driver.
• Support OpenMP SIMD IF clause.
• Added initial support of -lname processing when searching for fat static libraries.
• Added -fsycl-fp32-prec-sqrt flag which enables correctly rounded sycl::sqrt.
• Added support for [[intel::loop_count()]] attribute.
• Added support for passing driver options to JIT compiler and linker.
• Added default argument support for work_group_size_hint attribute.
• Added -f[no-]sycl-device-lib-jit-link option to control JIT linking of SYCL device libraries.
• Added support for the new FPGA attribute [[intel::fpga_pipeline(N)]] for loop pipelining. 
• Added support for sycl_ext_oneapi_properties extension.
• Added a mode for the Level Zero plugin where only the last command in each batch yields a host-visible event. Enabled this mode by default.
• Added support for an experimental Level Zero API for host pointer import into USM. The feature can be enabled using SYCL_USM_HOSTPTR_IMPORT environment variable.
• Added support for the wi_element for bf16 type. 
• Added complex support for the reduce and scan group algorithms. 
• Added SYCL_RT_WARNING_LEVEL environment variable which allows to control amount of warnings and performance hints the runtime library may print.
• Added support for USM buffer location properties that allows specifying at what memory location the device USM allocation should be in. 
• Added support for buffer_location property to the sycl::buffer.
• Added single_task support for ESIMD_EMULATOR backend. 
• Added support for SVM 1,2,4-elements gather/scatter for ESIMD.
• Added support for round-robin submissions to multiple compute CCS for the Level Zero backend. Disabled by default, can be controlled using SYCL_PI_LEVEL_ZERO_USE_COMPUTE_ENGINE. 
• Added support for buffer migration for contexts with multiple devices in the Level Zero plugin. 
• Added mode where the Level Zero plugin uses immediate command lists instead of standard command lists. This mode is disabled by default and can be enabled using SYCL_PI_LEVEL_ZERO_USE_IMMEDIATE_COMMANDLISTS environment variable. 
• Added reduction overloads accepting span.
• Added LSC support for ESIMD_EMULATOR backend.
• Added half type support for __esimd_convertvector_to/from.
• Added support for the USM buffer location property in malloc_shared. 
• Added support for the USM buffer location property in malloc_host. 
• Added support for memory intrinsics for the ESIMD_EMULATOR plugin.
• Added support for named barrier APIs for ESIMD.
• Added support for DPAS API for ESIMD.
• Added support for LSC memory access APIs for ESIMD.
• Added support for the invoke_simd feature. 
• Added support for info::device::atomic64 for OpenCL and Level Zero backends.
• Added support for sycl_ext_oneapi_usm_device_read_only extension.
• Added support for mapping/unmapping operations for the ESIMD_EMULATOR plugin.
• Added support for make_buffer API for the Level Zero backend.
• Added missing +-*/ operations for half. 
• Added ext_intel_global_host_space in accordance with sycl_ext_intel_usm_address_spaces extension. 
• Added aspect for bfloat16. 
• Introduced "Intel math functions" device library with support of type cast util functions for float, double, and integer types. 
• Added bfloat16 support for joint_matrix. 
• Added sycl_ext_oneapi_complex_algorithms extension. 
• Added sycl_ext_oneapi_group_load_store extension. 
• Added validation rules to the SPIR-V extension SPV_INTEL_global_variable_decorations. 
• Added SYCL_INTEL_buffer_location extension to support buffer_location property for USM allocations. 
• Added experimental latency control API into SYCL_INTEL_data_flow_pipes. 
• Added bfloat16 support to the fma, fmin, fmax and fabs SYCL floating point math functions into sycl_ext_oneapi_bfloat16 extension.
• Implemented property set generation for device globals in the sycl-post-link. Added the --device-globals command-line argument for lowering and generating information about device global variables. 
• Introduced XPTI-based tools for SYCL applications: sycl-trace, sycl-prof, sycl-sanitize.
• Add support for tracing Level Zero API calls using XPTI and updated sycl-trace tool to be able to display both PI and Level Zero calls simultaneously. 
• Added a diagnostic on an attempt to use zero-length arrays in the device code.
• Added support for consuming fat objects containing SPIR-V.
• Added support for generating SPRIV-based fat objects.
• Added a diagnostic on an attempt to use -fsycl and -static-libstdc++ together. This combination is not supported due to the runtime dependence with libsycl.so.
• Added support for atomic loads and stores with various memory orders and scopes.
• Improved performance of accessing memory pointed by sycl::accessor for FPGA device.
• Improved deferred diagnostics for usages within function templates in device code. 
• Added support for sycl_special_class attribute to mark SYCL classes/structs that needs the additional compiler handling.
• Improved driver to do device section checking only when offloading is enabled.
• Allowed calls to constant expression function pointers in device code.
• Disabled the passing code coverage and profiling options to device compilation.
• Added clang support of code location information for kernels.
• Disallowed explicit casts between mismatching address spaces.
• Added support of [[sycl::device_has]] attribute on the kernel.
• Added a warning on the explicit cast from default address space to name. 
• Added a warning for converting 'c' input to 'c++' in SYCL mode. 
• Silenced unknown attribute warnings on host compilation. 
• Added a diagnostic on an attempt to use accessor::operator[] in ESIMD code. 
• Expanded driver's ability to discover fat static archives after /link option on Windows. 
• Added support for saving user-specified names for lambda captures in kernel lambda object for FPGA target. 
• Adjusted the compilation when preprocessing is requested to allow for the device compilation to fail and continue to perform the preprocessing steps.
• Added the ability to detect a kernel size mismatch in the case when the host and device compilers are different.
• Improved handling of specialization constants by backends.
• Improved support of -mlong-double options. 
• Improved -save-temps to allow optimization when performing a SYCL device compilation. 
• Removed warning diagnostic on host compilation when using __attribute__((sycl_device)).
• Improved compiler to collect information for optimization record only if optimization record is saved by the user (i.e. -fsave-optimization-record or -opt-record-file is passed). 
• Improved [[intel::max_concurrency()]] attribute support. 
• Added the new kernel_arg_exclusive_ptr metadata which guarantees that the kernel pointer argument, or pointers that derive from it, will not be dereferenced outside the current invocation of the kernel. 
• Improved deprecation messaging for options.
• Improved diagnostic behavior for -fsanitize with -fsycl.
• Added support for sycl::ctz API [d5eb769]
• Improved the diagnostic for unresolved symbols in the device code for Level Zero backend.
• Added several arithmetic operations for sycl::ext::oneapi::experimental::wi_element.
• Added sycl::property_list APIs to sycl::stream. 
• Defined sycl::access::decorated in the SYCL headers. 
• Improved performance by allowing batching for the wait with barrier commands for Level Zero backend.
• Avoided JITing unnecessary device code when using sycl::handler::set_specialization_constant.
• Updated image accessor constructor to make it possible to use const references in parallel_for. 
• Relax the mutex lock duration in queue finish for the Level Zero backend to allow working with the queue from other threads. 
• Added XPTI instrumentation for USM allocations.
• Extended XPTI information with buffer constructor data.
• Added error handling for sycl::event::get_profiling_info().
• Eliminated recursion and duplicated dependencies in leaf buffers handling in the scheduler.
• Improved runtime to emit program build logs when SYCL_RT_WARNING_LEVEL is set to 2 or higher.
• Improved the error message at command execution failure.
• Improved runtime to build a program for root device only and re-use the binary for sub-devices to avoid "duplicate" builds. 
• Improved sycl::kernel::get_kernel_bundle performance. 
• Changed USM pooling parameters for the Level Zero backend to boost performance.
• Exposed value_type and min_capacity from SYCL pipes extension class. 
• Improved thread safety of the Level Zero plugin by guarding access to the PI objects.
• Improved runtime to redirect warnings from using SYCL_DEVICE_FILTER with sycl-ls to std::cerr.
• Use new SPIR-V group operations within uniform control flow instead of non-uniform operations in SYCL headers.
• Enabled online linking of the device libraries.
• Improved esimd-verifier logic for detecting valid SYCL calls.
• Extended XPTI information with the kernel info.
• Added overload for sycl::select(a, b, c) where c is a bool.
• Fixed batching-related thresholds to improve performance.
• Added always_inline for libdevice functions to enable which allows an underlying runtime to do inlining. 
• Improved performance by caching the result of zeKernelGetName in the Level Zero plugin.
• Updated the experimental latency control API to use property list and made the template argument approach deprecated.
• Enabled pooling of small USM allocations for the Level Zero backend to improve performance.
• Added managed memory check to enqueue prefetch, made it ignore the prefetch hint, and emit a warning if the memory provided is not managed. 
• Enabled device code instrumentation by default.
• Optimized host event wait.
• Improved default selector to filter devices based on available device images.
• Enabled caching of native OpenCL and Level Zero executable binaries.
• Deprecated sycl::ext::intel::ctz extension functionsycl::ctz from the core specification must be used instead.
• Deprecated ext_intel_host_device_space which is replaced by ext_intel_global_host_space.
• Added an option --enable-esimd-emulator to enable esimd emulator build using configure.py.
• Added an ability to build plugins separately.
• Added --enable-all-llvm-targets switch to configure.py. 
• Added PI tracing support for loadOsLibrary.
• Clarified the interaction between the sycl_ext_oneapi_invoke_simd extension and SYCL_EXTERNAL functions.
• Removed extensions specifications which were adopted to SYCL 2020. Please refer to extensions/removed/README for the list of removed extensions.
• Clarified which SPIR-V decorations the sycl-post-link tool generates for each device global variable.
• Updated the design for device global variables for variables that are "shadowed" in an unnamed namespace.
• Clarified the specification that device global with SYCL_EXTERNAL is allowed.
• Add an overview README for the extensions directory.
• Added a new rule for naming C++ identifiers in the SYCL project.
• Added ESIMD_EMULATOR to SYCL_DEVICE_FILTER description.
• Clarified availability of get_property().
• Deprecated extended atomics extension.
• Added description of ESIMD_EMULATOR backend to sycl_ext_intel_esimd/README.
• Added support for the task_sequence extension in FPGA.
• Modified the latency control APIs that apply to pipe read/write and LSU load/store in FPGA.
• Enhanced the FPGA optimization report GUI.
• Any support, addition, renew, removal, fix, or deprecation of any features in SYCL 2020 conformant, please check SYCL 2020 Specification Features. 

Bug Fixes

• There was a bug in DPC++/C++ compilers that they did not support linking library archives using the -l option for libraries that contain target offload code (i.e., offload code for GPU or FPGA). Instead of using the -l option, the linking command line had to specified the full path to the archive (file ending with .a). Furthermore, the developer had to guarantee that all required objects would be linked even if the libraries specified with the -l option were omitted from the command line. The simplest way to do this was to force linking of the whole archive. For example, if we assumed libbar.a in icx -o prog obj1.o obj2.o -L /path/to/libs -lfoo -lbar had target offload code, the command to link became icx -o prog obj1.o obj2.o -L /path/to/libs -lfoo -Wl,--whole-archive /path/to/libs/libbar.a -Wl,--no-whole-archive, where the -Wl,--no-whole-archive option was required after the user library even though no additional library was listed. This situation has been fixed for this release. 
• Fixed a crash that occurred if an overloaded new operator was used in a recursive function in the device code.
• Fixed macros being unavailable when using a custom host compiler. 
• Fixed device code linking when one of the targets is not spir64 based.[1f8874f]
• Disabled part of SimplifyCFG optimizations in SYCL mode resulted in invalid optimizations in some cases. 
• Silenced "unknown attribute" warning emitted during host part of full -fsycl compilation when it saw [[intel::device_indirectly_callable]] attribute. 
• Removed incorrect assertion for use of -fopenmp-new-driver for multiple inputs.
• Fixed problems where function pointers were captured as kernel arguments. [
• Fixed the error "Explicit load/store type does not match pointee type of pointer operand" caused by incorrect address space. 
• Fixed incorrect diagnostic for __spirv calls when the reqd_sub_group_size attribute is applied on a SYCL kernel. 
• Fixed alignment of emulated specialization constants. 
• Fixed a crash that could happen when building a program for multiple devices. 
• Fixed ambiguity error with sycl::oneapi::experimental::this_nd_item.
• Fixed a performance issue caused by unnecessary command batching in the Level Zero plugin.
• Fixed an issue that might result in JITing for only one device while context is associated with multiple devices for Level Zero backend.
• Fixed namespace ambiguity in this_id, this_item, and this_group. 
• Fixed two bugs in the Level Zero driver related to the static linking extension.
• Fixed return type of get_nativesycl::backend::opencl(event) from cl_event to vector<cl_event>. 
• Modified Level Zero plugin support for copy engines to address scenarios when the main copy engine is unavailable.
• Fixed support for the query of USM capabilities.
• Fixed memory leak in the USM prefetch functionality.
• Fixed host device local accessor alignment.
• Fixed sycl::errc values for exceptions per SYCL 2020. 
• Fixed bug with constexpr_recurse usage.
• Fixed max_work_group_size and reqd_work_group_size attribute arguments check.
• Fixed iterator debug level mismatch error on Windows when building programs with /MDd when libsycl-fallback-cassert.obj is involved.
• Fixed get_native() for sycl::event per requirements of the specification. 
• Fixed device enumeration for the next platforms when the current platform doesn't have devices. 
• Fixed thread-safety issue in the scheduler which can appear if a command gets cleaned up by another thread while adding a host accessor. 
• Fixed SYCL_PROGRAM_COMPILE_OPTIONS and SYCL_PROGRAM_LINK_OPTIONS to override compile and link options respectively.
• Fixed incorrect handling of queue indexing for Level Zero backend.
• Fixed memory leaks in the reductions that require additional resources (such as buffers).
• Defined get_property/has_property in the queue for property::queue::in_order. 
• Fixed memory leak in the scheduler for run_on_host_intel commands.
• Fixed thread-safety issue caused by parallel access to the command list cache in the Level Zero plugin. 
• Fixed device code outlining for static local variables to avoid invalid device code generation.
• Fixed dynamic batching in the Level Zero plugin.
• Fixed unsigned long warning in fallback cstring on Windows.
• Fixed sync of host task vs. kernel for the in-order queue.
• Fixed include dependency in fpga_lsu.hpp and pipes.hpp headers.
• Fixed kernel timestamp calculation in the Level Zero plugin. 
• Fixed usage of copy-engines in the Level Zero interoperability queue.
• Fixed kernel execution hangs under large memory consumption by workarounding a bug in the Level Zero runtime.
• Fixed the Level Zero plugin to honor property::queue::enable_profiling.
• Fixed memory leak which existed when program build failed for the Level Zero backend.
• Fixed buffer creation from rvalue iterator. 
• Fixed queue::device_has() to private.
• Fixed crash for the case when a device image has no kernels.
• Fixed dependency between host/device actions for unbundled FPGA-specific archives.
• Fixed interop_handle::get_native_mem so that it can work with accessors that use non-empty accessor_property_list. 
• Fixed sub-device count calculation for numa partitioning.
• Fixed SYCL_ENABLE_PLUGINS to enable both the OpenCL and the Level Zero PI plugins if it is unset. 
• Fixed BDF format on PCI query for the Level Zero backend.
• Fixed sycl::queue XPTI instrumentation.
• Fixed interoperability return type for sycl::buffer to std::vector<cl_mem> per SYCL 2020.
• Fixed SYCL_DUMP_IMAGES handling to also dump when spec constants are on. 
• Fixed failure in case of using zero-size local accessor on some backends.
• Fixed flaky bug which might appear in multi-threaded applications with simultaneous access to the cache of device lib programs.
• Fixed make_queue interoperability API for Level Zero to accept device argument to properly associate queue with the right device.
• Fixed invalid handler issue by updating OpenCL ICD loader from the community.
• Fixed "undefined symbol" error for ldexpf, hypotf, frexpf on SYCL GPU device using 3rd-party math headers instead of MSVC math headers on Windows.
• Fixed memory leak for interop events created from the native handle.
• Fixed alignment of the memory returned from USM allocation functions.
• Fixed sporadic failure of the in-order queue due to non-closed batch on the Level Zero backend.
• Fixed possible deadlock in case of having dependent events from different queues in a multi-threaded application.
• Fixed issue with the delivery of assert message before aborting.
• Fixed default value for the Alignment template parameter of the usm_allocator.
• Fixed API to get maximum width/height/depth of an image for the Level Zero backend.
• Fixed sycl-post-link tool to properly handle the offset in specialization constant descriptors.
• Fixed sycl-post-link tool to properly handle the padding at the end of composite types.
• Fixed translation of Vector[Extract/Insert]Dynamic instructions in llvm-spirv.
• Fixed unconditional debug info generation for libsycl_profiler_collector.so.
• Fixed sycl-post-link failure caused by incorrect removal of llvm.used in the case when specialization constant has 2+ users. 
• Removed extension to set kernel cache configuration. 
• Disallowed [[sycl_detail::uses_aspects()]] attribute on type aliases in OptionalDeviceFeatures. 
• Moved properties and property-related APIs into sycl::ext::oneapi::experimental. sycl_ext_oneapi_properties specification was updated to revision 2.
• Updated sycl_ext_oneapi_kernel_properties extension.
• Aligned sycl_ext_intel_kernel_args_restrict extension extension with SYCL 2020.
• Removed deprecated API from ESIMD headers.
• Renamed wi_slice to wi_data. 
• Renamed nbarrier_* API to named_barrier_* for ESIMD.
• Moved a part of ESIMD APIs outside of the experimental namespace. 
• Moved bfloat16 from intel namespace to oneapi namespace.
• Fixed an issue of FPGA compilation command option -Xsdsp-mode=<>, which used to fail when passed after some other -Xs command option.
• When compiling for FPGA, integer modulo operation for less than or equal to four bits ac_int and ac_fixed now uses 8-bits.
• Fixed an issue with FPGA optimization reports where the compiler did not render certain text characters included in the source file.
• Fixed an issue with FPGA compilation on a Linux system where the compiler could not detect the zlib library.

Known Issues and Limitations

• SYCL built-in group algorithms may produce wrong results on CPU or FPGA emulator devices if all of the following conditions are met:
  • The work-group size on the highest dimension is larger than the sub-group size
  • The group algorithm is applied to the work-group
  • The group algorithm produces same result for all work-items in the work-group (e.g. all_of_group, any_of_group, group_broadcast, reduce_over_group)
  • The group algorithm is used in a loop and the result may change due to change on inputs

For example, the following kernel code would produce wrong results (the while loop may not exit or acc[gid] may not be set for all work-items due to the known issue):

cgh.parallel_for(
  sycl::nd_range<1>(8, 8),
  [=](sycl::nd_item<1> item) [[intel::reqd_sub_group_size(4)]] { // work-group size > sub-group size
    bool predicate = true;
    int gid = item.get_global_id(0);
    while (sycl::all_of_group(item.get_group(), predicate)) { // applying all_of_group to the work-group
                                                              // and all_of_group is expected to produce same result for all work-items in the group
                                                              // and is used inside a loop
      acc[gid] = 1;
      predicate = false; // the result of all_of_group would change on the second loop iteration because predicate is changing
    }
  });

• SYCL 2020 barriers show worse performance than SYCL 1.2.1 do.
• It requires explicit linking against lib/libsycl-fallback-cassert.o or lib/libsycl-fallback-cassert.spvwhen using fallback assert in separate compilation flow.
• Limit alignment of allocation requests at 64KB which is the only alignment supported by Level Zero.
• On the following scenario on Level Zero backend:
  1. Kernel A, which uses buffer A, is submitted to queue A.
  2. Kernel B, which uses buffer B, is submitted to queue B.
  3. queueA.wait().
  4. queueB.wait(). DPCPP runtime is used to treat unmap/write commands for buffer A/B as host dependencies (i.e., they were waited for before enqueueing any command that's dependent on them). This allowed the Level Zero plugin to detect that each queue is idle on steps 1/2 and submit the command list immediately. This is no longer the case since we started passing these dependencies in an event waitlist and the Level Zero plugin attempts to batch these commands, so the execution of kernel B starts only on step 4. The workaround restores the old behavior in this case until this is resolved.
• User-defined functions with the name and signature matching those of any OpenCL C built-in function (i.e., an exact match of arguments, return type doesn't matter) can lead to Undefined Behavior.
• A DPC++ system that has FPGAs installed does not support multi-process execution. Creating a context opens the device associated with the context and places a lock on it for that process. No other process may use that device. Some queries about the device through device.get_info<>() also open up the device and lock it to that process since the runtime needs to query the actual device to obtain that information.
• The format of the object files produced by the compiler can change between versions. The workaround is to rebuild the application.
• Using sycl::program/sycl::kernel_bundle API to refer to a kernel defined in another translation unit leads to undefined behavior
• Linkage errors with the following message: error LNK2005: "bool const std::_Is_integral<bool>" (??$_Is_integral@_N@std@@3_NB) already defined can happen when a SYCL application is built using MS Visual Studio 2019 version below 16.3.0 and the user specifies -std=c++14 or /std:c++14.
• Printing internal defines is not supported on Windows.
• The usage of new -ax (auto cpu dispatch) is not currently supported when building libraries with -fpic option.
• /Fo<file or dir/> flag no longer accepts directory arguments. Using this flag will result in an error message: clang-offload-bundler command failed with exit code 1. Fix is not available in this release. 
• The compile times can be significant when compiling for FPGA and using a read-only accessor for a very wide struct. Using a read-write accessor instead is a workaround to address long compile times.
• When compiling for FPGA, you cannot use a system installed with Intel® FPGA PAC D5005 to compile a SYCL application that targets Intel® PAC with Intel® Arria® 10 FX FPGA. Compilation may succeed, but the compiled binary might fail at runtime. There is no workaround available for this issue currently.

• When you perform FPGA compile and link stages with a single dpcpp command (for example, dpcpp -fintelfpga <other arguments> -Xshardware src/kernel.cpp), if the source code is not located in the current directory, you might observe that the source code browser is missing in the generated FPGA optimization reports. To work around this issue, compile and link the executable in separate stages, as follows: 

  dpcpp -fintelfpga <other arguments> -Xshardware -c src/kernel.cpp -o kernel.o
  dpcpp -fintelfpga <other arguments> -Xshardware -kernel.o

• When compiling for FPGA, the debug support on Windows is unavailable when using device-side libraries. To avoid this issue, do not run a debugger on the emulator platform on Windows.

• In the FPGA optimization report, the Loop Viewer (Alpha) can only handle loops with 100 iterations or less currently. For designs with loops greater than 100 iterations, the optimization reports hang. There is no known workaround for this issue.

• The modulefiles-setup.sh script is not supported for FPGA in this release. As a workaround, use the setvars.sh script.

• On Windows, compiling FPGA designs in a directory with a long path name might fail, and you might see the following error:
  dpcpp: error: fpga compiler command failed with exit code 1 (use -v to see invocation)
  NMAKE : fatal error U1077: ‘…\oneAPI\compiler\latest\windows\bin\dpcpp.EXE' : return code '0x1'
  As a workaround, either compile the design in a directory with a short path name or reset TMP and TEMP environment variables to point to a shorter path (for example, C:\temp).

• When using the atomic_fence function for FPGA, the memory_scope::system constraint is not supported. The broadest scope supported is the memory_scope::device constraint. There is no workaround available for this currently.

• On Windows system, when compiling for FPGA emulator flow, using -c to create object files, linking through to an archive file, and generating an executable from that archive might result in an executable that fails to launch device kernels. As a workaround for this issue, add the -fsycl-device-code-split=none flag to the archive step as shown in the following:

  // generate .obj files
  dpcpp /EHsc -fintelfpga -c host.cpp device.cpp device_adder.cpp -DFPGA_EMULATOR
  // generate host.a
  dpcpp -fintelfpga -fsycl-link=image -fsycl-device-code-split=none host.obj device.obj device_adder.obj
  // generate .exe
  dpcpp -fintelfpga host.a /link /wholearchive
  // emulator executable
  host.exe

• When compiling for FPGA, the compiler might produce a different intermediate representation (IR) on Windows than Linux. Misaligned structs cause this issue. As a result, some designs that compile with an II=1 on Linux might have, for example, II=10 on Windows. As a workaround, force an alignment on the misaligned structs, as shown in the following example:

  //Code with misaligned struct
  struct Item {
    bool valid;
    int value1;
    unsigned char value2;
  };
  
  //Forced alignment of the struct
  struct Item {
    bool valid;
    bool __empty__[3];
    int value1;
    unsigned char value2;
    unsigned char __empty2__[3];
  }

   

   oneAPI 2022.2, Compiler Release 2022.1.0

oneAPI 2022.1, Compiler Release 2022.0.0

System Requirements

• Intel® oneAPI DPC++/C++ Compiler System Requirements

Additional Documentation

• Get Started with the Intel^® oneAPI Toolkits for Linux*
• Get Started with the Intel^® oneAPI Toolkits for Windows* 
• OneAPI Versioning Schema based on Semantic Versioning
• Intel® oneAPI DPC++/C++ Compiler Developer Guide and Reference

• SYCL* 2020 Specification Features and DPC++ Language Extensions Supported

• OpenMP* Features and Extensions Supported in Intel® oneAPI DPC++/C++ Compiler

Previous oneAPI Releases

• Intel® oneAPI DPC++/C++ Compiler 2021

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