Arria® 10 FPGA – Hello World on the Nios® V/m Processor Design Example

Arria® 10 FPGA – Hello World on the Nios® V/m Processor Design Example

839412
11/22/2024

Introduction

Nios® V/m-based Helloworld example design on the Intel® Arria® 10 FPGA.

Development Kit

Intel® Arria® 10 SX SoC Development Kits

Design Details

Device Family

Intel® Arria® 10 SX SoC FPGA

Intel® Arria® 10 SX 660 FPGA 10AS066N3F40E2SG
Quartus Edition

Intel® Quartus® Prime Pro Edition
Quartus Version

24.2
IP Cores (1)
IP Core IP Core Category
Nios® V/m Processor Intel FPGA IP Embedded Processor

Detailed Description

Please refer to the document for details about the design.

Prepare the design template in the Quartus Prime software GUI

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. You can simply double click on the <project>.par file and Quartus will launch that project.

Development Kit

Intel® Arria® 10 SX SoC Development Kits

Design Details

Device Family

Intel® Arria® 10 SX SoC FPGA

Intel® Arria® 10 SX 660 FPGA 10AS066N3F40E2SG
Quartus Edition

Intel® Quartus® Prime Pro Edition
Quartus Version

24.2