Arria® 10 FPGA – Simple Socket Server for the Nios® V/m Processor Design Example

Arria® 10 FPGA – Simple Socket Server for the Nios® V/m Processor Design Example

837384
10/28/2024

Introduction

This example design demonstrates communication with a telnet client on a development host PC.

Design Details

Device Family

Intel® Arria® 10 SX 660 FPGA 10AS066N3F40E2SG

Quartus Version

24.2

Other Tags

Validated in Quartus and Board

IP Cores (3)
IP Core IP Core Category
Nios V/m Processor Intel FPGA IP EmbeddedProcessor
Triple-Speed Ethernet Intel FPGA IP Ethernet
Transceiver ATX PLL Intel Arria 10/Cyclone 10 FPGA IP TransceiverPLL

Detailed Description

The telnet client offers a convenient way of issuing commands over a TCP/IP socket to the Ethernet-connected μC/TCP-IP running on the development board with a simple TCP/IP socket server example. The socket server example receives commands sent over a TCP/IP connection and turns LEDs on and off according to the commands. The example consists of a socket server task that listens for commands on a TCP/IP port and dispatches those commands to a set of LED management tasks.



Please refer to the document for details about the design.

Prepare the design template in the Quartus Prime software GUI

Note: The means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click ok and your design template will be installed. Click Cancel. Go to File -> Open. Double click on <project_name>.qar. The extracted quartus project file will be opened.

Design Details

Device Family

Intel® Arria® 10 SX 660 FPGA 10AS066N3F40E2SG

Quartus Version

24.2

Other Tags

Validated in Quartus and Board