Agilex™ 5 FPGA - Drive-On-Chip Design Example

Agilex™ 5 FPGA - Drive-On-Chip Design Example

825930
6/24/2024

Introduction

The design demonstrates synchronous control of up to two three-phase permanent magnet synchronous motors (PMSMs) or brushless DC (BLDC) motors
IP Cores (2)
IP Core IP Core Category
Nios V/g General Purpose Processor Processor
On Chip Memory Memory

Detailed Description

The design demonstrates synchronous control of up to two three-phase permanent magnet synchronous motors (PMSMs) or brushless DC (BLDC) motors. You can adapt the design to other motor types. The design includes a motor and power board model that removes the need for a physical motor setup. The design synthesizes and programs the model in the same FPGA. The model is a DSP Builder design.


You only need an Agilex™ 5 FPGA E-Series 065B Modular Development Kit to run the design. The motor and power board model helps to tune and test the control system before using a physical power stage.


Figure 1. High-Level Block Diagram of the Drive-on-Chip Design Example

The figure shows a top-level diagram of the design's hardware that demonstrates dual-axis control using an Intel® FPGA.