MAX® 10 FPGA - Helloworld on Nios® V/m Processor Design Example

MAX® 10 FPGA - Helloworld on Nios® V/m Processor Design Example

815406
12/11/2023

Introduction

Nios® V/m Processor-based Hello world design example on the MAX® 10 FPGA

Development Kit

Intel® MAX® 10 FPGA 10M50 Evaluation Kit DK-DEV-10M50F484-B

Design Details

Device Family

Intel® MAX® 10 10M50 FPGA 10M50DAF484C6GES
Quartus Edition

Intel® Quartus® Prime Standard Edition
Quartus Version

23.1
Other Tags

Validated in Quartus and Board
IP Cores (3)
IP Core IP Core Category
NIOS V/m soft processor core Embedded Processor
On Chip RAM Other
JTAG UART Other

Detailed Description

Please refer to the document for details about the design.

Prepare the design template in the Quartus Prime software GUI

Note: The means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click ok and your design template will be installed. Click Cancel. Go to File -> Open. Double click on <project_name>.qar. The extracted quartus project file will be opened.


Development Kit

Intel® MAX® 10 FPGA 10M50 Evaluation Kit DK-DEV-10M50F484-B

Design Details

Device Family

Intel® MAX® 10 10M50 FPGA 10M50DAF484C6GES
Quartus Edition

Intel® Quartus® Prime Standard Edition
Quartus Version

23.1
Other Tags

Validated in Quartus and Board