Introduction
| IP Core | IP Core Category |
|---|---|
| JESD204C Intel FPGA IP | Other |
| GPIO Intel FPGA IP | Other |
| Reset Release Intel FPGA IP | Other |
| IOPLL Intel FPGA IP | Other |
| JTAG to Avalon Master Bridge Intel FPGA IP | Other |
Detailed Description
This application note provides guidelines on how to scale up the single link of the JESD204C Intel® FPGA IP design example generated from the Intel® Quartus® Prime software to handle a dual link system. A single link in JESD204C has one or more high speed transceiver lanes or channels.
In some JESD204C applications, multiple analog-to-digital converters (ADCs) are used to sample the analog signals synchronously. Hence, synchronization between multiple converters in the array is required. In these applications, multiple converters interface with a single logic device, such as the Intel Agilex® 7 FPGA E-tile.
Before implementing the dual link design, you must generate the receiver (RX) single-link design example from the Intel® Quartus® Prime software. Intel® recommends that you perform an RTL simulation on this single link design example to confirm the functionality matches your expectation before transforming the design example to the dual link design. The guidelines in the following section assume the JESD204C parameters for each link in the dual link design are identical.
Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
Prepare the design template in the Quartus Prime software command-line
At the command-line, type the following command:
quartus_sh --platform_install -package <project directory>/<project>.par
Once the process completes, then type:
quartus_sh --platform -name <project>
Note:
* ACDS Version: 22.3.0 Pro