Agilex™ 7 – Custom Instruction on the Nios® V/g Processor Design Example

Agilex™ 7 – Custom Instruction on the Nios® V/g Processor Design Example

789373
6/16/2023
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Introduction

This design demonstrates the custom instruction feature of the Nios® V/g processor using Intel Agilex® 7 F-Series FPGA Development Kit

Development Kit

Intel Agilex® 7 FPGA F-Series Development Kit (Production 1 P-Tile & E-Tile) DK-DEV-AGF014EA

Design Details

Device Family

Intel Agilex® 7 FPGA F-Series 014 (R24B) AGFB014R24B2E2V
Quartus Edition

Intel® Quartus® Prime Pro Edition
Quartus Version

23.2
IP Cores (2)
IP Core IP Core Category
Nios V/g Processor Intel FPGA IP Embedded Processor
In-System Sources & Probes Intel FPGA IP Debug

Detailed Description

A Processing Engine (PE) that performs basic arithmetic and logical computations is connected to the Nios® V/g processor using the custom instruction interface. The current version of the Nios® V/g processor custom instruction interface supports operations up-to 32-Bit. 



Please refer to the document for details about the design.

Prepare the design template in the Quartus Prime software GUI

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. You can simply double click on the <project>.par file and Quartus will launch that project.

Development Kit

Intel Agilex® 7 FPGA F-Series Development Kit (Production 1 P-Tile & E-Tile) DK-DEV-AGF014EA

Design Details

Device Family

Intel Agilex® 7 FPGA F-Series 014 (R24B) AGFB014R24B2E2V
Quartus Edition

Intel® Quartus® Prime Pro Edition
Quartus Version

23.2